参数资料
型号: MIC5842YV
厂商: Micrel Inc
文件页数: 5/8页
文件大小: 0K
描述: IC DRVR LATCH 8BIT SER IN 20PLCC
标准包装: 48
类型: 锁存驱动器
输入类型: 非反相
输出数: 8
导通状态电阻: 50 千欧
电流 - 输出 / 通道: 500mA
电源电压: 5 V ~ 12 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-LCC(J 形引线)
供应商设备封装: 20-PLCC
包装: 管件
产品目录页面: 1091 (CN2011-ZH PDF)
其它名称: 576-1950-5
MIC5842YV-ND
Micrel, Inc.
MIC5841/42
Timing Conditions
(TA = 25°C Logic Levels are V DD and V SS ) V DD = 5V
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time)...................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................ 75 ns
C. Minimum Data Pulse Width ................................................................................................................................... 150 ns
D. Minimum Clock Pulse Width................................................................................................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ........................................................................................... 300 ns
F. Minimum Strobe Pulse Width.................................................................................................................................. 100 ns
G. Typical Time Between Strobe Activation and Output Transition............................................................................ 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the ENABLE input be high during serial data entry.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the
latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches.
MIC5840 Family Truth Table
Serial
Data
Input
Clock
Input
Shift Register Contents
I 1 I 2 I 3 … I 8
Serial
Data
Output
Strobe
Input
I 1
Latch Contents
I 2 I 3 …
I 8
Output
Enable
I 1
Output Contents
I 2 I 3 …
I 8
H
L
X
H
L
R1
R1
R1
R2
R2
R2
R3
R7
R7
R8
R7
R7
R8
X
X
X
X
X
L
R1
R2
R3
R8
P1
P2
P3
P8
P8
H
P1
P2
P3
P8
L
P1
P2
P3
P8
X
X
X
X
H
H
H
H
H
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
May 2006
5
M9999-050506
(408) 955-1690
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