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参数资料
| 型号： | MIC9131YQS |
| 厂商： | Micrel Inc |
| 文件页数： | 11/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DC-DC PWM HV HS 16-QSOP |
| 标准包装： | 98 |
| 应用： | 控制器，电信 |
| 输入电压： | 9 V ~ 18 V |
| 输出数： | 1 |
| 输出电压： | 4.7 V ~ 5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 管件 |
MIC9131
MIC9131
4μA
5V
Micrel, Inc.
SET
12
SS
S
Q
V IN
R1
R2
V CC
A GND
UVLO
2
11
13
1.21V
VCC
UVLO
LINE
UVLO
UVLO
R
RESET
/Q
15
16
OUT
PGND
Figure 4: UVLO and Soft Start Circuits
V LINE_ON = V THRESHOLD ×
V HYSTERESIS = V HYST ×
V CC Undervoltage Lockout
The V CC voltage is internally divided down and compared to
a 1.21V internal bandgap reference. As V CC rises above the
turn-on threshold, it disables the V CC undervoltage lockout
circuit. Once above the turn-on threshold, hysteresis prevents
the lockout circuit from disabling the IC until the V CC voltage
falls below the lower threshold.
Line Undervoltage Circuit (UVLO)
The line voltage is monitored by an external resistor divider
and fed into the negative input of the line UVLO comparator.
As the comparator trip point is exceeded, the line UVLO circuit
is disabled. Hysteresis built into the comparator prevents the
circuit from toggling on an off in the presence of noise or a
high input line impedance.
The line voltage turn-on trip point is:
R2
R1 + R2
where: V THRESHOLD is the voltage level of the internal
comparator reference, typically 1.21V.
The line hysteresis is equal to:
R1 + R2
R2
where: V HYST is the internal hysteresis level, typically
75mV.
V HYSTERESIS is the hysteresis of the line input
voltage
The MIC9131 will be disabled when the line voltage drops
back down to:
V LINE_OFF = V LINE_ON ? V HYTERESIS =
+
( V THRESHOLD ? V HYST ) × R1 R2 R2
Enable
A low level on the enable pin turns off all the functions of the
MIC9131 and places it in a low quiescent current state. The
output driver is in a low state. When the enable pin is pulled
high, the MIC9131 goes through its normal start up sequence
including undervoltage lock out and soft start. When not used,
the pin should be connected to V CC .
Oscillator Block
An external resistor and capacitor set the oscillator frequency.
The MIC9131 contains an internal divide-by-four circuit that
limits the maximum duty cycle at the gate drive to 75%. The
oscillator frequency of the MIC9131 is four times the output
switching frequency.
Oscillator Pin
The operation of the oscillator is shown in Figure 5. The volt-
age waveform at the OSC pin is a sawtooth whose amplitude
increases as capacitor Cosc is charged up through R OSC from
the 5V BIAS . When the OSC pin voltage reaches the internal
comparator upper threshold, C OSC is quickly discharged to
zero volts by an internal MOSFET. After a brief delay, typi-
cally 75ns, the internal MOSFET is turned off and the C OSC
charges, repeating the cycle. Figure 5 show the relationship
between the oscillator and gate drive waveforms. The delays
in the IC force the duty cycle of the gate drive signal to be
slightly less than 75% duty cycle.
For V BIAS = 5V and a peak oscillator waveform voltage of
3V, the design equations simplify to:
Charging
t CHARGE = 0 . 92 × R t × C t
Discharging
t DISCHARGE ≈ 40 × C t
August 2006
11
M9999-080206
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