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参数资料
| 型号： | MK1413SLFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 16.9344 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件页数： | 3/6页 |
| 文件大小： | 124K |
| 代理商： | MK1413SLFTR |
MPEG Audio Clock Source
MDS 1413 E
3
Revision 010606
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK1413
Application Information
Series Termination Resistor
Clock output traces should use series termination. For
series terminating a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the
clock line and as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Crystal Load Capacitors
The device crystal connections should include pads for
capacitors from X1 to ground and from X2 to ground,
and a parallel rsonant 14.31818 MHz crystal is
recommended. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. To reduce possible
noise pickup, use very short PCB traces (and no vias)
been the crystal and device.
The value (in pF) of each crystal load capacitor should
equal (CL -4) x2, where CL is the crystal’s load
(correlation) capacitance in pF. The frequency
tolerance of the crystal should be 50 ppm or better.For
a clock input, connect X1 and leave X2 unconnected.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed.
PCB Layout Recommendations
Observe the following guidelines for optimum device
performance and lowest output phase noise:
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI, and obtain the best signal integrity,
the 33
series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK1413. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
相关PDF资料 |
PDF描述 |
|---|---|
| MK2049-34SI | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-34SITR | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2762-01S | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2762-01STR | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2762-01STR | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK1413STR | 功能描述:IC AUDIO CLK SOURCE MPEG 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK1418 | 制造商:ICS 制造商全称:ICS 功能描述:OPL3, OPL4 + Codec Clock Source |
| MK1418S | 制造商:ICS 功能描述: |
| MK1418STR | 制造商:ICS 制造商全称:ICS 功能描述:OPL3, OPL4 + Codec Clock Source |
| MK14-1A66B-100W | 制造商:MEDER 制造商全称:Meder Electronic 功能描述:MK Reed Sensors |
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