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参数资料
| 型号： | MK1415SLF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 33 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | SOIC-8 |
| 文件页数： | 3/4页 |
| 文件大小： | 42K |
| 代理商： | MK1415SLF |
MK1415
ESS Notebook Sound Clock Source
MDS1415A
3
Revision 1237
Printed 10/15/99
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
ICRO
CLOCK
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Typical values are at 25°C.
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+.5V
V
Clock Outputs
Referenced to GND
-0.5
VDD+.5V
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (at 5.0V unless otherwise noted)
Operating Voltage, VDD
3.0
5.5
V
Input High Voltage, VIH, input clock only
3.5
2.5
V
Input Low Voltage, VIL, input clock only
2.5
1.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-4mA
VDD-0.4
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Operating Supply Current, IDD, 5.0V
No Load
14
mA
Operating Supply Current, IDD, 3.3V
No Load
8
mA
Power Down Supply Current, IDDPD, 5V
No Load
10
A
Input Capacitance
PD pin
7
pF
AC CHARACTERISTICS (at 5.0V unless otherwise noted)
Input Clock
14.31818
MHz
Power up time, from power down to clocks stable PD low to high
4
10
ms
Input Clock Duty Cycle
Time above 2.5V
20
80
%
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
Time above 1.5V
45
50
55
%
Absolute Maximum Clock Period Jitter
Variation from mean
130
ps
One Sigma Clock Period Jitter
40
ps
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