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参数资料
| 型号： | MK1415STRLF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 33 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | SOIC-8 |
| 文件页数： | 2/4页 |
| 文件大小： | 42K |
| 代理商： | MK1415STRLF |
MK1415
ESS Notebook Sound Clock Source
MDS1415A
2
Revision 1237
Printed 10/15/99
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
ICRO
CLOCK
1
ICLK
I
Input CLOCK. Connect to a 14.31818 MHz clock.
2
VDD
P
Connect to +3.3V or +5V.
3
GND
P
Connect to ground.
4
33.0M
O
33.00 MHz clock output.
5
GND
P
Connect to ground.
6
VDD
P
Connect to +3.3V or +5V. Connect to pin 2.
7
PD
I
Power Down. Active low. Both output clocks stop low.
8
14.3M
O
14.31818 MHz buffered clock output.
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
Pin Assignment
External Components/Crystal Selection
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.1F should be connected between VDD and GND on pins 2 and 3, and a 33
terminating resistor
should be used on each clock output if the trace is longer than 1 inch.
1
8
2
3
4
7
6
5
ICLK
PD
GND
14.318M
VDD
GND
MK1415
33.0M
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