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参数资料
| 型号： | MK1417SLF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 27 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8 |
| 封装： | SOIC-8 |
| 文件页数： | 2/4页 |
| 文件大小： | 29K |
| 代理商： | MK1417SLF |
MK1417
S3 Notebook Clock Source
MDS1417B
2
Revision 12157
Printed 12/16/97
MicroClock division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
Number
Name
Type
Description
1
X1/ICLK
I
Crystal Connection. Connnect to a 14.31818 MHz crystal or clock.
2
VDD
P
Connect to +3.3V or +5V.
3
GND
P
Connect to ground.
4
14.3M
O
14.31818 MHz buffered crystal clock output.
5
14.3M
O
14.31818 MHz buffered crystal clock output.
6
27M
O
27.00 MHz clock output.
7
PD
I
Power Down input. Logic 0 takes all clocks low. Internal pullup.
8
X2
O
Crystal Connection for a 14.31818 MHz crystal, or leave unconnected for clock input.
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
Pin Assignment
External Components/Crystal Selection
A minimum number of external components are required for proper operation. For a crystal input, a
parallel resonant 14.31818 MHz crystal is recommended. The frequency tolerance of the crystal should be
±30 ppm maximum. For tuning with a given crystal CL, the formula 2(CL-6) gives the value of each
capacitor that should be connected from X1 to GND and X2 to GND. For a clock input, connect to X1
and leave X2 unconnected. A decoupling capacitor of 0.1F should be connected between VDD and
GND on pins 2 and 3, and a 33
terminating resistor can be used on each clock output if the trace is
longer than 1 inch.
1
8
2
3
4
7
6
5
X1/ICLK
GND
X2
VDD
14.3M
8 pin SOIC
14.3M
27M
PD
All Clocks
0
LOW
1
ON
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