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参数资料
| 型号： | MK14223LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 33.868 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | SOIC-8 |
| 文件页数： | 2/4页 |
| 文件大小： | 56K |
| 代理商： | MK14223LF |
MK14223
3.3V Audio Codec Clock Source
MDS14223C
2
Revision 8048
Printed 8/6/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Number
Name
Type
Description
1
X1/ICLK
I
Crystal Connection. Connect to a 14.318 MHz crystal or clock.
2
VDD
P
Connect to +3.3V or +5V.
3
GND
P
Connect to ground.
4
16.9M
O
16.9344 MHz clock output for stereo codec.
5
24.6M
O
24.576 MHz clock output for stereo codec.
6
33.9M
O
33.868 MHz clock output for OPL4.
7
PD
I
Power Down. Shuts off entire chip when low. All clock outputs stop low.
8
X2
O
Crystal Connection to a 14.318 MHz crystal, or leave unconnected for clock input.
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
Pin Assignment
1
8
2
3
4
7
6
5
X1/ICLK
VDD
GND
16.9M
X2
PD
33.9M
24.6M
14.318 MHz in
Pin 1
33
(optional)
2
3
5
6
7
0.1F
16.9MHz out
24.6MHz out
G
V
33
(optional)
Suggested Layout
4
8
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. For a crystal input, one
22pF load capacitor should be connected to each of the X1 and X2 pins and ground, and a parallel
resonant 14.318 MHz, 16pF load, crystal is recommended. Values near these are acceptable, as is a series
resonant crystal, but either will result in frequencies which are slightly (up to 0.06%) different from the
ideal. For a clock input, connect to X1 and leave X2 unconnected. A decoupling capacitor of 0.1F should
be connected between VDD and GND, and 33
terminating resistors may be used on the clock outputs.
These termination resistors are unnecessary for clock traces less than 1” (25mm).
33
(optional)
33.9MHz
out
PD
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