参数资料
型号: MK14223TRLF
元件分类: 时钟产生/分配
英文描述: 33.868 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: SOIC-8
文件页数: 3/4页
文件大小: 56K
代理商: MK14223TRLF
MK14223
3.3V Audio Codec Clock Source
MDS14223C
3
Revision 8048
Printed 8/6/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Typical values are at 25°C.
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+.5V
V
Clock Outputs
Referenced to GND
-0.5
VDD+.5V
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 20 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS
Operating Voltage, VDD
2.97
5.5
V
Input High Voltage, VIH, X1/ICLK
VDD/2 + 1
VDD/2
V
Input Low Voltage, VIL, X1/ICLK
VDD/2
VDD/2 - 1
V
Input High Voltage, VIH, PD
2
V
Input Low Voltage, VIL, PD
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH
IOH=-4mA
VDD-0.4
V
Output Low Voltage, VOL
IOL=4mA
0.4
V
Operating Supply Current, IDD, 3.3V
No Load
15
mA
Power Down Operating Current, IDDPD, 3.3V No Load
20
A
Input Capacitance
7
pF
Actual Mean Frequency versus Target
Outputs
±0.05
%
AC CHARACTERISTICS
Input Clock Frequency
14.31818
MHz
Input Clock Duty Cycle, 14.318MHz
Time above VDD/2
20
80
%
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle, 24.576MHz
Time above VDD/2
45
50
55
%
Output Clock Duty Cycle, 16.9344 MHz
Time above VDD/2
45
50
55
%
Output Clock Duty Cycle, 33.868MHz
Time above VDD/2
45
50
55
%
Absolute Clock Period Jitter
Pins 4, 5, 6 only
-400
200
400
ps
One Sigma Clock Period Jitter
Pins 4, 5, 6 only
60
ps
相关PDF资料
PDF描述
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