
MK1432/MK1434
Green PC and Local Bus Clock Source
MDS 1432 G
3
Revision 060101
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800 www.icst.com
Electrical Specifications
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. With 2XCPU clock at 66.66MHz, and BCLK at 33.33MHz
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 20 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5V unless noted)
Operating Voltage, VDD
3.0
5.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Mid-level pin Input High Voltage, VIH
Pin 9 only
VDD-0.5
V
Mid-level pin Input Low Voltage, VIL
Pin 9 only
0.5
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH
VDD=3.3V, IOH=-8mA
2.4
V
Output Low Voltage, VOL
VDD=3.3V, IOL=8mA
0.4
V
Operating Supply Current, IDD
No Load, note 2
40
mA
Operating Supply Current, IDDPS
No Load, PS=0
27
mA
Short Circuit Current
Each output (except X2)
±100
mA
On-Chip Pull-up Resistor
Pins 1, 8, 10, 16
250
k
Input Capacitance
7
pF
AC CHARACTERISTICS (VDD = 5V unless noted)
Input Frequency
14.31818
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
45
49 to 51
55
%
Cycle to Cycle Jitter, CPU Clocks
1000
ps
Absolute Clock Period Jitter
14-40 MHz clocks
-500
500
ps
Skew of 2XCPU with respect to CPU
Rising edges at 1.5V
-250
0
250
ps
Transition time, 33.3MHz to 66.6MHz
VDD=3.3 or 5V
3
ms
Transition time, 66.6MHz to 33.3MHz
VDD=3.3 or 5V
2
ms
External Components
The MK1432/4 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.1F should be connected between VDD and GND, as close to the MK1432/4 as possible. A series termination
resistor of 33
may be used for each clock output. The device does not require (nor do we recommend) capacitors
connected to the crystal pins. The 14.31818 MHz crystal must be connected as close to the chip as possible.
Recommended load capacitance for the crystal is 12pF.