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参数资料
| 型号： | MK1492-02RLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, SSOP-28 |
| 文件页数： | 3/7页 |
| 文件大小： | 70K |
| 代理商： | MK1492-02RLF |
MK1492-02
Intel Mobile/SDRAM Clock Source
MDS1492-02E
3
Revision 2028
Printed 2/2/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
ICRO
CLOCK
Electrical Specifications
External Components
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 2)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Operating Voltage, VDD
3.0
3.3
3.6
V
Operating Voltage, VDD
2.5/3.3
VDD
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-8mA
2.4
V
Output Low Voltage, VOL
IOL=8mA
0.4
V
Output High Voltage, VOH
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, 66.6MHz
62
mA
Power Down mode Supply Current
3
Α
Short Circuit Current
Each output
±50
mA
Input Capacitance
7
pF
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Frequencies
14.318
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle, all MHz clocks
At 1.5V
45
49 to 51
55
%
HOST3:8 Output to Output Skew
Rising edges at 1.5V
250
ps
Skew of HOST 1,2 with respect to HOST 3:8
250
ps
PCI Output to Output Skew
Rising edges at 1.5V
500
ps
Lead of HOST outputs with respect to PCI
Rising edges at 1.5V
1
1.75
4
ns
Cycle to Cycle Jitter, CPU Clocks
250
ps
Absolute Clock Period Jitter, Other MHz Clocks
-500
500
ps
EMI reduction, peaks of 5th - 19th odd harmonics
66.6 MHz HOST clock
6
11
dB
Power up time, CPUS# going high to all clocks stable
8
20
ms
Power on time, applied VDD to all clocks stable
12
25
ms
Note 2.
Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels
above the operating limits but below the Absolute Maximums may affect device reliability.
HOST1,2 or 3,4
The MK1492 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1F should be connected on
each VDD pin to ground, as close to the MK1492 as possible. A series termination resistor of 33
may be used for each clock output. See the
discussion on page 7 for other external resistors required for proper I/O operation.
The 14.3 MHz oscillator has internal caps that provide the
proper load for a parallel resonant crystal with CL=12pF. For tuning with other values of CL, the formula 2*(CL-12) gives the value of each
capacitor that should be connected between X1 and ground and X2 and ground.
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