参数资料
型号: MK1493-02AG
元件分类: 时钟产生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封装: 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件页数: 13/24页
文件大小: 444K
代理商: MK1493-02AG
Networking/PCI Clock Generator
MDS 1493-02A C
20
Revision 020204
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
MK1493-02A
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70
°C, C
L = 10 - 30 pF
Shared Pin Operation - Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power up, they
act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a five-bit
internal data latch. At the end of Power-on resent, (see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output
function. In this mode, the pins produce the specified
buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed
during the power-up programming period and to provide
an insignificant load on the output clock during the
subsequent operation period.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper
installed, the pin will be pulled high. With the jumper in
place, the pin will be pulled low. If programmability is not
necessary, then only a single resistor is necessary. The programming resistors should be located close to the
series termination resistor to minimize the current loop area. It is more important to place the series termination
resistor close to the driver than to the programming resistor.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Output Impedance
RDSP
VO = VDD*0.5
20
60
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
Output High Current
IOH
VOH@MIN = 1.0 V, VOH @MAX =
3.135 V
-29
-23
mA
Output Low Current
IOL
VOH@MIN = 1.95 V, VOH @MAX =
0.4 V
29
27
mA
Rise Time
TRISE
VOL = 0.4 V, VOH = 2.4 V
2
ns
Fall Time
TFALL
VOH = 2.4 V, VOL = 0.4 V
1.8
ns
Duty Cycle
dt
VT = 1.5 V
45
55
%
Skew
tSK
VT = 1.5 V
70
ps
Jitter
VT = 1.5 V
1000
ps
Device
Pad
Series Term. Res.
Clock trace to load
8.2K
2K
Via to
VDD
Programming
Header
Via to GND
Figure 1
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