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参数资料
| 型号： | MK1575-01GI |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件页数： | 1/12页 |
| 文件大小： | 217K |
| 代理商： | MK1575-01GI |
MK1575-01
MDS 1575-01 L
1
Revision 070605
Integrat ed Circuit Systems ● 525 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m
CLOCK RECOVERY PLL
Description
The MK1575-01 is a clock recovery Phase-Locked
Loop (PLL) designed for clock synthesis and
synchronization in cost sensitive applications. The
device is optimized to accept a low-frequency
reference clock to generate a high-frequency data or
graphics pixel clock. External loop filter components
allow tailoring of loop frequency response
characteristics. For low jitter / phase noise
requirements refer to the MK2069 products.
Features
Long-term output jitter <2 nsec over 10 sec period
External PLL clock feedback path enable “zero
delay” I/O clock skew configuration
Selectable internal feedback divider provides popular
telecom and video clock frequencies (see tables
below)
Can optionally use external feedback divider to
generate other output frequencies.
Single 3.3 V supply, low-power CMOS
Power-down mode and output tri-state (pin OE)
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Industrial temperature range available
Pre-Configured Input/Output
Frequency Combinations:
Telecom T/E Clock Modes (rising edge aligned):
Video Clock Modes (falling edge aligned):
Block Diagram
The standard external clock feedback configuration is shown. Use this configuration for the pre-configured
input/output frequency combinations listed above.
Addr
FS2:0
Input
Clock
Output Clocks
(MHz)
Clock
Type
CLK1
CLK2
000
8 kHz
3.088
1.544
T1
001
8 kHz
16.384
2.048
E1
010
8 kHz
34.368
17.184
E3
011
8 kHz
44.736
22.368
T3
Addr
FS2:0
Input
Clock
(kHz)
Output Clocks
(MHz)
Clock
Type
CLK1
CLK2
100
15.625
54
27
PAL 601
101
15.734
54
27
NTSC 601
110
15.625
35.468
17.734
PAL 4xfsc
111
15.734
28.636
14.318
NTSC 4xfsc
REFIN
FBIN
CLK1
Clock Input
MUX
0
1
Charge
Pump
VCO
CHGP
VS
Divider
Phase
Detector
CHPR
MUX
0
1
C
B
R
S
C
S
FCLK
Divider
CLK2
Divider
LUT
CLK2
FCLK
FS2:0
3
External Feedback Clock Connection
OE
300 pF
相关PDF资料 |
PDF描述 |
|---|---|
| MK1575-01G | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MK1575-01GITR | 1575 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MK1707SLFTR | 1707 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| MK1707STR | PLL BASED CLOCK DRIVER, PDSO8 |
| MK1707STR | PLL BASED CLOCK DRIVER, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK1575-01GILF | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1575-01GILFTR | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1575-01GITR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MK1575-01GLF | 功能描述:时钟发生器及支持产品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1575-01GLFTR | 功能描述:时钟发生器及支持产品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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