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参数资料
| 型号： | MK1581-01GILF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC CLK GENERATOR T1/E1 16-TSSOP |
| 标准包装： | 96 |
| 类型： | 时钟发生器 |
| PLL： | 无 |
| 输入： | 时钟，晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 2.048MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
MK1581-01
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
VCXO AND SYNTHESIZER
IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR
5
MK1581-01
REV F 051310
A “normalized” PLL loop bandwidth may be calculated as
follows:
The “normalized” bandwidth (NBW) equation above does
not take into account the effects of damping factor or the
second pole. NBW is approximately equal to the actual -3dB
bandwidth of the loop when the damping factor is about 5
and C2 is very small. In most applications, NBW is about
75% of the actual -3dB bandwidth. However, NBW does
provide a useful approximation of filter performance.
The loop damping factor is calculated as follows:
Where:
RS = Value of resistor in loop filter (Ohms)
ICP = Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
CS = Value of capacitor CS in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components CS and CP in the loop
filter:
Charge Pump Current Table
Special considerations must be made in choosing loop
components CS and CP.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a commonly
used trace impedance), place a 33
resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
. (The
optional series termination resistor is not shown in the
External Component Schematic.)
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK1581-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK1581-01 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
NBW
RS ICP
×
575
×
N
-----------------------------------------
=
Damping Factor
RS
625
I
CP
×
CS
×
N
-------------------------------------------
×
=
CP
CS
20
------
=
RSET
Charge Pump Current
(ICP)
1.4 M
10
A
680 k
20
A
540 k
25
A
120 k
100
A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK1581-01GILFTR | 功能描述:时钟发生器及支持产品 LOW PHASE NOISE T1/E 1 CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK1581-01GITR | 功能描述:IC CLK GENERATOR T1/E1 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK159 | 制造商:Velleman Inc 功能描述:Brain Game Kit |
| MK15-B-0 | 制造商:MEDER 制造商全称:Meder Electronic 功能描述:MK Reed Sensors |
| MK15-B-0_DE | 制造商:MEDER 制造商全称:Meder Electronic 功能描述:(deutsch) MK Reed Sensor |
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