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参数资料
| 型号： | MK1604-01STR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 40.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 2/4页 |
| 文件大小： | 45K |
| 代理商： | MK1604-01STR |
MK1604
Low Cost Video CD Clock Source
MDS1604C
2
Revision 12037
Printed 12/3/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Number
Name
Type Description
1
X1/ICLK
I
Crystal connection. Connect to 16.9344 MHz crystal, or clock input
2
VDD
P
Connect to +3.3V or +5V. Must be same as other VDDs.
3
VDD
P
Connect to +3.3V or +5V. Must be same as other VDDs.
4
PD
I
Power Down. Stops 40.5, 27 and 13.5 MHz clocks low when taken low.
5
GND
P
Connect to ground.
6
GND
P
Connect to ground.
7
13.5M
O
13.5 MHz clock output.
8
27M
O
27.00 MHz clock output.
9
CCLK
O
Controller Clock output. Determined by CCS0, CCS1 per Table above.
10
CCS1
I
Controller Clock Select 1. Determines CCLK output per Table above.
11
CCS0
I
Controller Clock Select 0. Determines CCLK output per Table above.
12
40.5M
O
40.5 MHz clock output.
13
16.9344M
O
16.9344 MHz buffered crystal oscillator output.
14
16.9344M
O
16.9344 MHz buffered crystal oscillator output.
15
NC
-
No Connect.
16
X2
O
Crystal connection. Leave unconnected for clock input, or connect to 16.9344 MHz crystal.
Pin Descriptions
Type: I = Input, O = output, P = power supply connection
Pin Assignment
1
16
2
3
4
15
14
13
VDD
GND
X2
16 pin narrow (150 mil) SOIC
5
6
7
8
12
11
10
9
16.9344M
13.5M
X1/ICLK
40.5M
NC
CCS1
CCS0
27M
CCLK
CCS1
CCS0
CCLK
pin 10 pin 11
pin 9
0
Test
0
M
23 MHz
0
1
11.5 MHz
M
0
16 MHz
M
4 MHz
M
1
8 MHz
1
0
32.5 MHz
1
M
20 MHz
1
10 MHz
Controller Clock
Decoding Table
VDD
PD
GND
16.9344M
M = mid level. The inputs are self-biased to this level
when the pins are left unconnected. 0 or 1 means to
connect directly to ground or VDD, respectively.
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