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参数资料
| 型号： | MK1726-01S |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 32 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 3/8页 |
| 文件大小： | 205K |
| 代理商： | MK1726-01S |
MK1726-01A
LOW EMI CLOCK GENERATOR
SSCG
IDT / ICS LOW EMI CLOCK GENERATOR
3
MK1726-01A
REV C 052804
External Components
The MK1726-01A requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 7 and 2, as close to these
pins as possible. For optimum device performance, the
decoupling capacitor should be mounted on the component
side of the PCB. Avoid the use of vias in the decoupling
circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50
trace (a commonly used trace impedance)
place a 33
resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20
.
Tri-level Select Pin Operation
The S1, S0 select pins are tri-level, meaning they have three
separate states to make the selections shown in the table on
page 2. To select the M (mid) level, the connection to these
pins must be eliminated by either floating them originally, or
tri-stating the GPIO pins which drive the select pins.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) To minimize EMI, the 33
series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK1726-01A. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (CL - 6) x 2
In the equation, CL is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Spread Spectrum Profile
The MK1726-01A low EMI clock generator uses an
optimized frequency slew rate algorithm to facilitate down
stream tracking of zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant with
variations of the input frequency.
Time
Fr
eq
ue
nc
y
Modulation Rate
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