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参数资料
| 型号： | MK2049-02LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 3/6页 |
| 文件大小： | 87K |
| 代理商： | MK2049-02LF |
MK2049-02
Communications Clock PLL
MDS2049-02
3
Revision 7309
Printed 7/30/99
MicroClock Division of ICS 525 Race Street San Jose CA 95126 (408)295-9800tel(408)295-9818fax
ICRO
CLOCK
ADVANCE
ADVANCE INFORMATION
INFORMATION
0 = connect directly to ground, 1 = connect directly to VDD.
Crystal is connected to pins 2 and 3; clock input is applied to pin
13.
Output Decoding Table – External Mode (MHz)
ICLK
FS3 FS2 FS1 FS0
CLK1
CLK2
Crystal
Zero Delay
ICLK to CLK2
8 kHz
0
1.544
3.088
12.352
No
8 kHz
0
1
2.048
4.096
12.288
No
8 kHz
0
1
0
22.368
44.736
11.184
Yes
8 kHz
0
1
17.184
34.368
11.456
Yes
8 kHz
0
1
0
19.44
38.88
12.96
Yes
8 kHz
0
1
0
1
16.384
32.768
8.192
Yes
8 kHz
0
1
0
24.576
49.152
12.288
Yes
8 kHz
0
1
25.92
51.84
12.96
Yes
8 kHz
1
0
10.24
20.48
10.24
Yes
8 kHz
1
0
1
4.096
8.192
12.288
No
ICLK
FS3 FS2 FS1 FS0
CLK1
CLK2
Crystal
Zero Delay
ICLK to CLK2
1.544
1
0
1.544
3.088
12.352
No
2.048
1
0
1
2.048
4.096
12.288
No
44.736
1
0
1
0
22.368
44.736
11.184
Yes
34.368
1
0
1
17.184
34.368
11.456
Yes
Output Decoding Table – Loop Timing Mode (MHz)
ICLK
FS3 FS2 FS1 FS0
CLK1
CLK2
Crystal
Zero Delay
ICLK to CLK2
19 - 28
1
0
ICLK/2
ICLK
ICLK/2
Yes
10 - 14
1
2*ICLK
4*ICLK
ICLK
Yes
Output Decoding Table – Buffer Mode (MHz)
Operating Modes
The MK2049-02 has three operating modes: External, Loop Timing, and Buffer. Although each mode
uses an input clock to generate various output clocks, there are important differences in their input and
crystal requirements.
External Mode
The MK2049-02 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse
as narrow as 10 ns is acceptable.
Loop Timing Mode
This mode can be used to remove the jitter from a high-frequency input clock. For T1 and E1 inputs, the
CLK1 output will be the same as the input frequency, with CLK2 at twice the input frequency. For T3
and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the input frequency.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-02S | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLLs |
| MK2049-02SI | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLLs |
| MK2049-02SITR | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLLs |
| MK2049-02STR | 制造商:ICS 制造商全称:ICS 功能描述:Communications Clock PLLs |
| MK2049-03S | 制造商:MICROCLOCK 功能描述: |
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