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参数资料
| 型号： | MK2049-45ASI |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.300 INCH, SOIC-20 |
| 文件页数： | 4/9页 |
| 文件大小： | 181K |
| 代理商： | MK2049-45ASI |
3.3 Volt Communications Clock PLL
MDS 2049-45A A
4
Revision 110305
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK2049-45A
the MK2049-45A is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low frequency
reference clock.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
Application Information
Output Frequency Configuration
The MK2049-45A is configured to generate a set of
output frequencies from an 8 kHz input clock. Please
refer to the Output Clock Selection Table on Page 2.
Input bits FS3:0 are set according to this table, as is the
external crystal frequency. Please refer to the Quartz
Crystal section on this page regarding external crystal
requirements.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the MK2049-45A. Failure to do so may result
in reduced frequency pullability range, inability of the
loop to lock, or excessive output phase jitter.
The MK2049-45A operates by phase-locking the
VCXO circuit to the input signal of the selected ICLK
input. The VCXO consists of the external crystal and
the integrated VCXO oscillator circuit. To achieve the
best performance and reliability, a crystal device with
the recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The MK2049-45A incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the MK2049-45A are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK2049-45A and the
crystal.
To obtain a list of qualified crystal devices please visit
our website.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The MK2049-45A uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
2) The loop filter values can be user selected to
optimize loop response characteristics for a given
application.
Referencing the External Component Schematic on
this page, the external loop filter is made up of
components RS, CS and CP. RSET establishes PLL
charge pump current and therefore influences loop
filter characteristics.
Tools for optimizing the values of these four
components can be found on our web site.
CAP2
CAP1
0.0003 F
820 kohms
0.1 F
Figure 3. Typical Loop Filter
R
S
C
P
C
S
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2049-45ASILF | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2049-45ASILFTR | 功能描述:时钟发生器及支持产品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2049-45ASITR | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-45SI | 功能描述:IC CLK PLL COMM 3.3V 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2049-45SILF | 功能描述:时钟合成器/抖动清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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