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| 型号： | MK2058-01SILF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC VCXO CLK JITTER ATTEN 20-SOIC |
| 标准包装： | 37 |
| 类型： | 时钟振动衰减器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 27MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
| 其它名称： | 800-2262 MK2058-01SILF-ND |
MK2058-01
COMMUNICATIONS CLOCK JITTER ATTENUATOR
VCXO AND SYNTHESIZER
IDT COMMUNICATIONS CLOCK JITTER ATTENUATOR
3
MK2058-01
REV G 051310
Functional Description
The MK2058-01 is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase-Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2058-01 is configured
to provide an output clock that is the same frequency as the
input clock. There are 12 selectable input / output frequency
ranges, each of which is a submultiple of the supported
quartz crystal frequency range. Please refer to the Output
Clock Selection Table on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2058-01 is able to
generate a low jitter, low phase-noise output clock within a
low bandwidth PLL. This serves to provide input clock jitter
attenuation and enables stable operation with a
low-frequency reference clock.
The VCXO circuit requires an external pullable crystal for
operation. External loop filter components enable a PLL
configuration with low loop bandwidth.
Application Information
Input / Output Frequency Configuration
The MK2058-01 is configured to generate an output
frequency that is equal to the input reference frequency.
Clock frequencies that are supported are those which fall
into the ranges listed in the Output Clock Selection Table on
Page 2. Input bits SEL2:0 are set according to this table, as
is the external crystal frequency. The nominal (center)
frequency of the external crystal will be an integer multiple
of the input / output clock as specified. Please refer to the
Quartz Crystal section on this page regarding external
crystal requirements.
Input Mux
The Input Mux serves to select between two alternate input
reference clocks. Upon reselection of the input clock, clock
glitches on the output clock will not be generated due to the
“fly-wheel” effect of the VCXO (the quartz crystal is a high-Q
tuned circuit). When the input clocks are not phase aligned,
the phase of the output clock will change to reflect the phase
of the newly selected input at a controlled phase slope (rate
of phase change) as influenced by the PLL loop
characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK2058-01. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK2058-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK2058-01 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK2058-01 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK2058-01 and the crystal.
A complete description of the recommended crystal
parameters is in application note MAN05.
A list of approved crystals is located on the IDT web site.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating
stability. The MK2058-01 uses external loop filter
components for the following reasons:
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2058-01SILFTR | 功能描述:时钟合成器/抖动清除器 COMMUNICATIONS CLOCK JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK205801SITR | 制造商:Integrated Device Technology Inc 功能描述: |
| MK2058-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2059-01 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Frame Clock Frequency Translator |
| MK2059-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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