- 您现在的位置：买卖IC网 > PDF目录45328 > MK2069-01GI (INTEGRATED DEVICE TECHNOLOGY INC) 160 MHz, OTHER CLOCK GENERATOR, PDSO56 PDF资料下载
参数资料
| 型号： | MK2069-01GI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件页数： | 7/21页 |
| 文件大小： | 411K |
| 代理商： | MK2069-01GI |
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
15
MK2069-01
REV K 051310
Circuit Troubleshooting
1) IF TCLK or VCLK does not lock to ICLK
First check VCLK to ICLK. It is best to display and trigger the
scope with RCLK, especially if a non-integer VCXO PLL
multiplication ratio is used.
If VCLK is not locked to ICLK:
1.1) Ensure the proper ICLK input is selected.
1.2) Check RV, SV, FV Divider settings
1.3) Ensure ICLK is within lock range (within about 100 ppm
of the nominal input frequency, limited by pull range of the
external crystal). If in doubt, tweak the ICLK frequency up
and down to see if VCLK locks.
1.4) Ensure ICLK jitter is not excessive. If ICLK jitter is
excessive device may not lock. Also see item 2.1 below.
1.5) Clean the PCB. The VCXO PLL loop filter is very
sensitive to board leakage, especially when the VCXO PLL
phase detector frequency is in the low kHz. If organic solder
flux is used (most common today) scrub the PCB board with
detergent and water and then blow and bake dry. Inorganic
solder flux (Rosen core) requires solvent. See also section
3 below.
2) If There is Excessive Jitter on VCLK or TCLK
2.1) The problem may be an unstable input reference clock.
An unstable ICLK will not appear to jitter when ICLK is used
as the oscilloscope trigger source. In this condition, VCLK
and TCLK may appear to be unstable since the jitter from
ICLK (the trigger source) has been removed by the trigger
circuit of the scope.
2.2) The instability may be caused by VCXO PLL loop filter
leakage. Refer to item 1.5 above.
2.3) VCLK and TCLK jitter can also be caused by poor
power supply decoupling. Ensure a bulk decoupling
capacitor is in place.
2.4) Ensure that the VCXO PLL loop bandwidth is
sufficiently low. It should be at least 1/20th of the phase
detector frequency.
2.5) Ensure that the VCXO PLL loop damping is sufficient.
If should be at least 0.7, preferably 1.0 or higher.
2.6) Ensure that the 2nd pole in the VCXO PLL loop filter is
set sufficiently. In general, CP should be equal to CS/20. If
CP is too high, passband peaking will occur and loop
instability may occur. If CP is set too low, excessive VCXO
modulation by the charge correction pulses may occur.
3) If There is Excessive Input to Output Skew
3.1) TCLK should track VCLK. The rising edge of TCLK
should be within a few nanoseconds of VCLK.
3.1) VCLK should track RCLK. The rising edge of VCLK
should be within 5-10 nsec of RCLK (VCLK leads).
3.3) The biggest cause of input to output skew is VCXO PLL
loop filter leakage. Skew is best observed by comparing
ICLK to RCLK. When no leakage is present the rising edge
of RCLK should lag the rising edge of ICLK by about 10
usec. Loop filter leakage can greatly increase this lag time
or cause the loop to not lock. Refer to item 1.5, above.
3.4) Another way to view the loop filter leakage is to observe
LDR pin. Use RCLK as the scope trigger. LDR will produce
a negative pulse equal in length to the charge pump pulse.
3.5) Filter leakage can also be caused by the use of
improper loop capacitors. Refer to the section titled ‘Loop
Filter Capacitor Type’ on page 9.
相关PDF资料 |
PDF描述 |
|---|---|
| MK2069-02GILF | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK2069-02GITR | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK2069-02GILFTR | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK2069-02GILFTR | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| MK2069-03GITR | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2069-01GILF | 功能描述:时钟合成器/抖动清除器 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK2069-01GILFTR | 功能描述:时钟发生器及支持产品 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2069-01GITR | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2069-03 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。