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参数资料
| 型号： | MK2069-01GILFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件页数： | 1/19页 |
| 文件大小： | 344K |
| 代理商： | MK2069-01GILFTR |
MK2069-01
MDS 2069-01 H
1
Revision 050203
Integr at ed Circuit Sy stems l 5 25 Race Street, San Jose, CA 9 512 6 l tel (40 8 ) 2 95-98 00 l
VCXO-Based Line Card Clock Synchronizer
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable,
jittery input clock and provide a de-jittered, low phase
noise output clock at a user determined frequency. The
device’s clock multiplication ratios are user selectable
since all major PLL divider blocks can be configured
through device pin settings. External PLL loop filter
components allow tailoring of the VCXO PLL loop
response and therefore the clock jitter attenuation
characteristics.
The MK2069-01 is ideal for line card applications. Its
three input MUX enables selection of the master or
slave (backup) system clocks, as well as a backup local
line card clock. The lock detector (LD) output serves as
a clock status monitor. The clear (CLR) input enables
rapid synchronization to the phase of a newly selected
input clock, while eliminating the generation of extra
clock cycles and wander caused by memory in the PLL
feedback divider. CLR also serves as a temporary
holdover function when kept low.
Features
Input clock frequency of 1kHz to 170MHz
Output clock frequency of 500kHz to 160MHz
Jitter attenuation of input clock provided by VCXO
circuit. Jitter transfer characteristics user configured
through selection of external loop filter components.
3:1 Input MUX for input reference clocks
PLL lock status output
PLL Clear function allows seamless synchronizing to
an altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
VCXO-based clock generation offers very low jitter
and phase noise generation, even with a low
frequency or jittery input clock.
2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies
(TCLK).
Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
56 pin TSSOP package
Single 3.3V power supply
5V tolerant inputs on ICLK0 and ICLK1
Block Diagram
C harge
Pum p
VC XO
P u lla b le
xtal
VC LK
X2
X1
IS E T
4
VD D
4
CL R
LF
FV D iv ide r
1 -4096
RV
Div id e r
1,2 ,4,12 8
SV
Div id e r
1,2,4,6,8,
10,1 2 ,1 6
IC L K 2
IC L K 1
MX 1 :0
0X
RV 1 :0
2
RT
Div id e r
1-4
Phase
De tecto r
VC X O
PL L
FT D iv id e r
1-64
ST
Div id e r
2,4 ,8,16
VC O
T ran slato r
PLL
SV 2 :0
3
F V 11:0
FT5 :0
6
ST1 :0
2
TC LK
OE V
OE T
IC L K 0
10
01
2
LD
OE L
GN D
RCL K
OE R
L o c k D e te cto r
12
LD C
LD R
LFR
RT 1 :0
2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2069-01GITR | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2069-03 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| MK2069-03GITR | 功能描述:时钟发生器及支持产品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK2069-04 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Universal Clock Translator |
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