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参数资料
| 型号： | MK2069-04GILFTR |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC VCXO CLK TRANSLATOR 56-TSSOP |
| 标准包装： | 1,000 |
| 类型： | 时钟同步器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 带卷 (TR) |
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
18
MK2069-04
REV J 051310
Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may
result in increased output phase noise.
Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the
attempt of the PLL to lock to 0 Hz.
Note 3: The minimum practical phase detector frequency is 1 kHz. Through proper loop filter design lower input
frequencies may be possible. Input frequencies as low as 400 Hz have been tested.
Note 4: A higher input clock frequency can be used when RPV divider = 8.
Note 5: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period.
Note 6: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the
external VCXO PLL loop filter.
Output Rise Time, VCLK and
RCLK
tOR
0.8 to 2.0 V, CL=15 pF
1.5
2
ns
Output Fall Time, VCLK and
RCLK
tOF
2.0 to 0.8 V, CL=15 pF
1.5
2
ns
Output Rise Time, TCLK
tOR
0.8 to 2.0 V, CL=15 pF
0.75
1
ns
Output Fall Time, TCLK
tOF
2.0 to 0.8 V, CL=15 pF
0.75
1
ns
Skew, ICLK to VCLK (Note 6)
tIV
Rising edges, CL=15 pF
-5
2.5
+10
ns
Skew, ICLK to RCLK (Note 6)
tIV
Rising edges, CL=15 pF
+5
10
+20
ns
Skew, ICLK to TCLK (Note 6)
tVT
Rising edges, CL=15 pF
-5
1.5
+10
ns
Nominal Output Impedance
ZOUT
20
Ω
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2069-04GITR | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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