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参数资料
| 型号： | MK2731-01GLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 64 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 2/6页 |
| 文件大小： | 134K |
| 代理商： | MK2731-01GLF |
LOW COST VCXO
MDS 2731-01 E
2
Revision 021804
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
MK2731-01
Pin Assignment
Output Clock Select Table
(All OFF outputs are stopped low)
Pin Descriptions
12
1
11
2
10
3
9
X2
4
X1
5
VDD
6
NC
7
VIN
8
GND
S2
VDD
GND
CLK2
S0
OE
S1
16
15
14
13
CLK1
VDD
16-pin narrow (150 mil) SOIC
Input
S2
S1
S0
CLK1
CLK2
10
0
40
80
10
0
1
40
OFF
13.5
0
1
0
40
OFF
13.5
0
1
27
54
13.5
1
0
33.33
66.66
13.5
1
0
1
24.576
49.152
—
1
0
Test use
13.5
1
32
64
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X2
Output
Crystal connection. Connect to a 10 or 13.5 MHz pullable crystal.
2
X1
Input
Crystal connection. Connect to a 10 or 13.5 MHz pullable crystal.
3
VDD
Power
Connect to +5 V.
4
VIN
Input
Voltage input to VCXO. Zero to 3 V signal which controls the
VCXO frequency.
5
GND
Power
Connect to ground.
6
GND
Power
Connect to ground.
7
OE
Input
Output Enable. Active high. Tri-states both outputs when low.
8
CLK1
Output
Clock output 1 determined by status of S2, S1, and S0. See table
above.
9
S0
Input
Fixed Clock Select 0. Selects outputs per table above.
10
S1
Input
Fixed Clock Select 1. Selects outputs per table above.
11
CLK2
Output
Clock output 2 determined by status of S2, S1, and S0. See table
above.
12
GND
Power
Connect to ground.
13
VDD
Power
Connect to +5 V.
14
S2
Input
Fixed Clock Select 2. Selects outputs per table above.
15
NC
--
No connect.
16
VDD
Power
Connect to +5 V.
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