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参数资料
| 型号： | MK2731-02SLFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 117 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 3/4页 |
| 文件大小： | 43K |
| 代理商： | MK2731-02SLFTR |
MK2731-02A
Low Cost VCXO
MDS2731-02AD
3
Revision 12037
Printed 12/3/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
4.75
5.25
V
Input High Voltage, VIH, X1 pin only
3.5
2.5
V
Input Low Voltage, VIL, X1 pin only
2.5
1.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, note 2
24
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
S2, S1, S0, OE
7
pF
Frequency synthesis error
All clocks
0
ppm
VIN, VCXO control voltage
0
3
V
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Crystal Frequency
12.288 or 13.5
MHz
Input Crystal Accuracy
±30
ppm
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
60
%
Maximum Absolute Jitter, short term
200
ps
27 MHz output pullability, note 3
0V
≤ VIN ≤ 3V
±100
ppm
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With CLK1, CLK3 = 27MHz, and CLK2 = 54MHz.
3. With a MicroClock approved pullable crystal.
External Components
The MK2731-02 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND on pins 3 and 5, as close to the
MK2731-02 as possible. A series termination resistor of 33
may be used for each clock output. The input
crystal must be connected as close to the chip as possible. The input crystal should be a parallel mode,
pullable, AT cut, with 14pF load capacitance. Consult MicroClock for recommended suppliers.
IMPORTANT - consult the application note MAN05 for layout guidelines.
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