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参数资料
| 型号： | MK2731-02STR |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 117 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 2/4页 |
| 文件大小： | 43K |
| 代理商： | MK2731-02STR |
MK2731-02A
Low Cost VCXO
MDS2731-02AD
2
Revision 12037
Printed 12/3/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Pin Descriptions
Key: I = Input, O = output, P = power supply connection, VI = analog voltage input
Pin Assignment
Number
Name
Type
Description
1
X2
XO
Crystal connection. Connect to a pullable 12.288 or 13.5 MHz crystal.
2
X1
XI
Crystal connection. Connect to a pullable 12.288 or 13.5 MHz crystal.
3
VDD
P
VDD. Connect to +5V.
4
VIN
VI
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
5
GND
P
Connect to ground.
6
GND
P
Connect to ground.
7
OE
I
Output Enable. Active high. Tri-states all outputs when low.
8
CLK1
O
Clock output 1 determined by status of S2, S1, S0. See table above.
9
S0
I
Clock Select 0. Selects outputs per table above.
10
S1
I
Clock Select 1. Selects outputs per table above.
11
CLK2
O
Clock output 2 determined by status of S2, S1, S0. See table above.
12
NC
-
No Connect. Nothing is connected internally to this pin.
13
CLK3
O
Clock output 3 determined by status of S2, S1, S0. See table above.
14
S2
I
Clock Select 2. Selects outputs per table above.
15
NC
-
No Connect. Nothing is connected internally to this pin.
16
VDD
P
Connect to +5V.
Output Clock Select Table (MHz)
16
15
14
13
16 pin narrow (150 mil) SOIC
12
11
10
9
1
2
3
4
5
6
7
8
MK2731-02
VDD
GND
X2
X1
VIN
CLK1
GND
OE
S1
S0
CLK2
NC
VDD
S2
Input
S2
S1
S0
CLK1
CLK2
CLK3
12.288
0
Off
98.304
Off
12.288
0
1
28.672
Off
12.288
0
1
0
3.584
Off
13.5
0
1
19.5
117
Off
13.5
1
0
19.44
Off
13.5
1
0
1
27
54
27
13.5
1
0
27
13.5
1
27
Off
CLK3
NC
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