参数资料
型号: MK2732-06GLFTR
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 54 MHz, VIDEO CLOCK GENERATOR, PDSO16
封装: 0.173 INCH, LEAD FREE, TSSOP-16
文件页数: 2/8页
文件大小: 192K
代理商: MK2732-06GLFTR
MK2732-06
LOW PHASE NOISE VCXO AND MULTIPLIER
VCXO AND SYNTHESIZER
IDT LOW PHASE NOISE VCXO AND MULTIPLIER
2
MK2732-06
REV H 051310
Pin Assignment
Clock Select Table
0 = connect directly to ground
M=leave unconnected (floating)
1 = connect directly to VDDIO
off=output stopped low
Pin Descriptions
Key: TI = tri-level input; VI = analog voltage input; XI, XO = crystal pins
1
2
3
GND
4
VDD5
5
6
REFCLK
7
8
NC
GND
S0
S1
X2
GND
CLK1
VDD5
16
X1
VIN
OE
VDDIO
CLK2
15
14
13
12
11
10
9
16-pin (173 mil) TSSOP
S1
S0
Input
CLK1
CLK2
REFCLK
0
13.248
52.992
35.238
OFF
0
M
13.248
35.238
OFF
0
1
13.248
35.238
ON
M
0
13.248
52.992
35.238
ON
M
13.5
54
27
OFF
M
1
13.554
27ON
1
0
13.527
54ON
1
M
Test mode
1
13.527
27ON
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1
XI
Crystal connection. Connect to a pullable crystal of 10 to 14.318 MHz.
2 , 3
VDD5
Power
Core VDD. Connect to +5 V.
4
VIN
VI
Voltage input to VCXO. Zero to 3 V signal which controls the frequency of the
VCXO.
5, 6, 13
GND
Power
Connect to ground.
7
S1
TI
Select input #1. Selects the outputs per table above. Do not exceed VDDIO.
8
OE
Input
Output Enable. Tri-states outputs when low. Do not exceed VDDIO.
9
CLK1
Output
Clock output #1 per table above. Amplitude = VDDIO.
10
S0
TI
Select input #0. Selects the outputs per table above. Do not exceed VDDIO.
11
VDDIO
Power
Input and output VDD. Connect to 3.3. V or 5 V. Clock amplitude matches this
voltage.
12
CLK2
Output
Clock output #2 per table above. Amplitude = VDDIO.
14
NC
Nothing connected internally to this pin.
15
REFCLK
Output
Buffered crystal VCXO clock.
16
X2
XO
Crystal connection. Connect to a pullable crystal of 10 to 14 MHz.
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