参数资料
型号: MK2745-24SILFT
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 0.150 INCH, SOIC-16
文件页数: 2/6页
文件大小: 137K
代理商: MK2745-24SILFT
DVD/MPEG CLOCK SOURCE
MDS 2745-24 D
2
Revision 042904
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 297-1 201 www.icst.com
MK2745-24
Pin Assignment
Feedback Configuration Table
Output Clock Mode Select Table
Pin Descriptions
1
2
3
GND
4
CLKA1
5
6
CLKA4
7
8
CLKA3
VDD
CLKB3
CLKB2
FBIN
CLKB1
S1
CLKA2
16
CLKIN
VDD
S2
CLKB4
GND
15
14
13
12
11
10
9
16-pin (150 mil) SOIC
Feedback From
CLKA1:A4
CLKB1:B4
Bank A
CLKIN
CLKIN/2
Bank B
2XCLKIN
CLKIN
S2
S1
Clocks A1:A4
Clocks B1:B4
Internet Generation
PLL Status
0
Tri-state (high impedance)
None
On
0
1
Running
Tri-state (high impedance)
PLL
On
1
0
Running
Buffer only (no zero delay)
Off
1
Running
PLL
On
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
CLKIN
Input
Clock input. Connect to input clock source.
2, 3
CLKA1:A4
Output
Clock A bank of four outputs.
4
VDD
Power
Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V).
5
GND
Power
Connect to ground.
6, 7
CLKB1:B4
Output
Clock B bank of four outputs. These are low skew divide by two of bank A.
8
S2
Input
Select input 2. Selects mode for outputs per table above.
9
S1
Input
Select input 1. Selects mode for outputs per table above.
10, 11
CLKB1:B4
Output
Clock B bank of four outputs. These are low skew divide by two of bank A.
12
GND
Power
Connect to ground.
13
VDD
Power
Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V).
14, 15
CLKA1:A4
Output
Clock A bank of four outputs.
16
FBIN
Input
Feedback input. Determines outputs per table above.
相关PDF资料
PDF描述
MK2745-24ST PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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