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参数资料
| 型号： | MK2762-01SLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 1/4页 |
| 文件大小： | 24K |
| 代理商： | MK2762-01SLF |
MK2762
MPEG/Set-Top Clock Source
MDS2762B
1
Revision 5307
Printed 7/25/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
The MK2762 is a low cost, low jitter, high
performance clock synthesizer for Zoran Dolby
AC3, MPEG, and set-top box based applications.
Using analog Phase-Locked Loop (PLL)
techniques, the device accepts a 27.00 MHz crystal
or clock input to produce multiple output clocks
including 33 MHz, 13.5 MHz, a selectable audio
clock, and three low-skew copies of the 27 MHz
input. The audio clocks are frequency locked to
the 27.00 MHz input with zero ppm error,
allowing audio and video to track exactly, thereby
eliminating the need for large buffer memory.
MicroClock manufactures the largest variety of
Set-Top Box and multimedia clock synthesizers
for all applications. Consult MicroClock to
eliminate crystals and oscillators from your board.
Description
Features
Packaged in 16 pin narrow (150 mil) SOIC
Zero ppm audio clock error for 256X and 128X
Selectable audio sampling frequencies support
32 kHz, 44.1 kHz, and 48 kHz in most DACs
27.00 MHz crystal or clock input
Fixed clocks of 27, 13.5, and 33.3 MHz
Zero ppm error in all output clocks
25mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
5V±10% operating voltage
See also the MK2712 for NTSC/PAL clocks
Block Diagram
Crystal
Oscillator
VDD
GND
Clock Synthesis
and Control
Circuitry
33.3333 MHz
Output
Buffer
27.00 MHz
clock or crystal
Output
Buffer
Output
Buffer
ACLK/2
Output
Buffer
ACLK
Output
Buffer
27.0000 MHz
Output
Buffer
13.5000 MHz
X2
X1
27.0000 MHz
Output
Buffer
27.0000 MHz
Output
Buffer
27.0000 MHz
(180° Phase Shift)
AS0
AS1
2
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相关代理商/技术参数 |
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