2. This specification includes the 2% precision of the internal reference frequency (slow clock).
3. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
4. This specification was obtained at TBD frequency.
5. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
6. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
7. This specification was obtained at internal frequency of TBD.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator Electrical Characteristics
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC Electrical Specifications
Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VDD33OSC 3.3 V supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode
32 kHz
1 MHz
4 MHz
8 MHz
16 MHz
24 MHz
32 MHz
—
500
100
200
300
700
1.2
1.5
—
nA
μA
mA
IDDOSC
Supply current — high gain mode
32 kHz
1 MHz
4 MHz
8 MHz
16 MHz
24 MHz
32 MHz
—
25
200
400
800
1.5
3
4
—
μA
mA
Cx
EXTAL load capacitance
—
Cy
XTAL load capacitance
—
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
26
Preliminary
Freescale Semiconductor, Inc.
Preliminary