参数资料
型号: MK3200GLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 0.032768 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 3 MM, LEAD FREE, MSOP-8
文件页数: 3/8页
文件大小: 192K
代理商: MK3200GLFT
MK3200
32.768 KHZ CLOCK OSCILLATOR
32 KHZ OSCILLATOR
IDT 32.768 KHZ CLOCK OSCILLATOR
3
MK3200
REV G 051310
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a commonly
used trace impedance), place a 33
resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the MK3200
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI, the 33
series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK3200. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
4) The input crystal must be connected as close to the chip
as possible. The input crystal should be a parallel mode
crystal with a 12 pF load capacitance.
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