参数资料
型号: MK3200SLF
厂商: IDT, Integrated Device Technology Inc
文件页数: 3/8页
文件大小: 0K
描述: IC CLOCK OSC 32.768KHZ 8-SOIC
标准包装: 97
类型: 时钟振荡器
PLL:
输入: 晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 无/无
频率 - 最大: 32.768kHz
除法器/乘法器: 无/无
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
其它名称: 800-2005-5
MK3200SLF-ND
MK3200
32.768 KHZ CLOCK OSCILLATOR
32 KHZ OSCILLATOR
IDT 32.768 KHZ CLOCK OSCILLATOR
3
MK3200
REV H 073012
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
Ω trace (a commonly
used trace impedance), place a 33
Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the MK3200
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI, the 33
Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK3200. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
4) The input crystal must be connected as close to the chip
as possible. The input crystal should be a parallel mode
crystal with a 12 pF load capacitance.
相关PDF资料
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