参数资料
型号: MK3727HLFTR
元件分类: 时钟产生/分配
英文描述: 36 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, GREEN, SOIC-8
文件页数: 3/6页
文件大小: 128K
代理商: MK3727HLFTR
LOW DRIVE 3.3 VOLT VCXO
MDS 3727H E
3
Revision 041906
Integ rated Ci rcuit Systems
525 R a ce S t reet, Sa n Jose, CA 95126
tel (4 08) 297-1 201
www. icst.com
MK3727H
External Component Selection
The MK3727H requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD (pin 2) and GND (pin 4 & 7), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
Use series termination when the PCB trace between
the clock outputs and the loads are over 1 inch. To
series terminate a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
Quartz Crystal
The MK3727H VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (as described in application
note MAN05) must be used, and the layout guidelines
discussed in the following section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3727H incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3727H is designed to have zero frequency
error when the total of on-chip + stray capacitance is
14 pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3727H. There should be no vias
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3727H to 3.3 V. Connect pin
3 of the MK3727H to the second power supply. Adjust
the voltage on pin 3 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3 V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25 ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS MicroClock for details.) If the
centering error is more than 25 ppm positive, add
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
Error
10
6x
f3.0V ftet
arg
()
f0V ftet
arg
()
+
ftet
arg
------------------------------------------------------------------------------
errorxtal
=
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