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参数资料
| 型号： | MK3732-10SLFTR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 162 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 3/7页 |
| 文件大小： | 105K |
| 代理商： | MK3732-10SLFTR |
VCXO AND MULTIPLIER
MDS 3732-10 B
3
Revision 120202
Int egrat ed C i rcuit Syste ms q 525 R a ce S t r eet, San Jose, CA 95126 q t e l (40 8 ) 295 -9800 q
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MK3732-10
Pin Descriptions
The MK3732-10 requires a minimum number of
external components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between VDD and GND on pins 2 and 5 and pins 3 and
6, as close to the MK3732-10 as possible. For optimum
device performance, the decoupling capacitors should
be mounted on the component side of the PCB. Avoid
the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs (CLK,
pin 5) and the loads are over 1 inch, series termination
should be used. To series terminate a 50
trace (a
commonly used trace impedance) place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Quartz Crystal
The MK3732-10 VCXO function consists of the
external crystal and the integrated VCXO oscillator
circuit. To assure the best system performance
(frequency pull range) and reliability, a crystal device
with the recommended parameters (shown below)
must be used, and the layout guidelines discussed in
the following section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3732-10 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3732-10 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF.
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
XI
Crystal connection. Connect to a pullable of 16 to 28 MHz cyrstal.
2 - 3
VDD
Power
Connect to +3.3 V.
4
VIN
Input
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency.
5 - 6
GND
Power
Connect to ground.
7
S3
Input
Select input #3. Selects outputs per table above. Internal pull-up resistor.
8
S2
Input
Select input #2. Selects outputs per table above. Internal pull-up resistor.
9
PDCLK3
Input
Power down for CLK3.
10
S0
Input
Select input #0. Selects outputs per table above. Internal pull-up resistor.
11
CLK3
Output
PLL output clock that is either a multiple of the input or an audio clock. See table
above.
12
REF
Output
Buffered VCXO reference clock output. Matches crystal frequency.
13
REF/2
Output
Reference clock output divided by two.
14
S1
Input
Select input #1. Selects outputs per table above. Internal pull-up resistor.
15
OE
Input
Output enable. Tri-states outputs when low. Internal pull-up resistor.
16
X2
XO
Crystal connection. Connect to a pullable 16 to 28 MHz crystal.
相关PDF资料 |
PDF描述 |
|---|---|
| MK3732-10SLF | 162 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-10STR | 162 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-10S | 162 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-15GTRLF | 108 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| MK3732-15GTR | 108 MHz, OTHER CLOCK GENERATOR, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK3732-10STR | 功能描述:IC VCXO/MULTIPLIER 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK3732-17 | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17S | 功能描述:时钟合成器/抖动清除器 ADSL VCXO CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK3732-17SI | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17SITR | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
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