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参数资料
| 型号： | MK3732-17S |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | IC VCXO CLK SOURCE ADSL 16-SOIC |
| 标准包装： | 48 |
| 类型： | PLL 时钟合成器，VCXO |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 49.46MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
MK3732-17
ADSL VCXO CLOCK SOURCE
VCXO AND SYNTHESIZER
IDT / ICS ADSL VCXO CLOCK SOURCE
3
MK3732-17
REV D 050803
External Component Selection
The MK3732-17 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between VDD and GND on pins 3 and 6, and on pins 13 and
14, as close to the MK3732-17 as possible. For optimum
device performance, the decoupling capacitors should be
mounted on the component side of the PCB. Avoid the use
of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50
trace (a commonly used trace
impedance) place a 33
resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20
.
Quartz Crystal
The MK3732-17 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To assure
the best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters must be used, and the layout guidelines
discussed in the following section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3732-17 incorporates on-chip variable load capacitors
that “pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3732-17 is designed to have
zero frequency error when the total of on-chip + stray
capacitance is 14pF.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the MK3732-17. There should be no vias between the
crystal pins and the X1 and X2 device pins. There should be
no signal traces underneath or close to the crystal.
Please see application note MAN05 for recommended
crystal parameters and suppliers.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of your final
layout, a frequency counter capable of about 1 ppm
resolution and accuracy, two power supplies, and some
samples of the crystals which you plan to use in production,
along with measured initial accuracy for each crystal at the
specified crystal load capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3732-17 to 3.3V. Connect pin 4 of
the MK3732-17 to the second power supply. Adjust the
voltage on pin 4 to 0V. Measure and record the frequency of
the CLK output.
2. Adjust the voltage on pin 4 to 3.3V. Measure and record
the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal being
measured
If the centering error is less than ±25 ppm, no adjustment is
needed. If the centering error is more than 25ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact ICS for details.) If the
centering error is more than 25ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
Error
10
6
x
f3.3V ftet
arg
–
()
f
0V
f
tet
arg
–
()
+
f
tet
arg
------------------------------------------------------------------------------
error
xtal
–
=
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK3732-17SI | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17SITR | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17STR | 功能描述:时钟合成器/抖动清除器 ADSL VCXO CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK3732-19GLF | 制造商:Integrated Device Technology Inc 功能描述:MK3732-19GLF - Bulk |
| MK3732-19GLFTR | 制造商:Integrated Device Technology Inc 功能描述:MK3732-19GLFTR - Tape and Reel |
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