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参数资料
| 型号： | MK3732-17STR |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 49.46 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 2/7页 |
| 文件大小： | 203K |
| 代理商： | MK3732-17STR |
MK3732-17
ADSL VCXO CLOCK SOURCE
VCXO AND SYNTHESIZER
IDT / ICS ADSL VCXO CLOCK SOURCE
2
MK3732-17
REV D 050803
Pin Assignment
Clock Select Table
0=connect directly to GND
M=leave unconnected (floating)
1=connect directly to VDD
Pin Descriptions
12
1
11
2
10
3
9
X2
4
X1
5
VD D
6
DC
7
VIN
8
NC
GN D
VD D
NC
GN D
S0
S2
CLK1
O E
16
15
14
13
CLK2
S1
16 Pin (150 m il) S O IC
S2
S1
S0
Input
CLK1
CLK2
0
13.248
35.328
29.4
0
M
13.248
35.328
47.1
0
1
13.248
35.328
40.4
0
1
0
13.248
42.4
35.328
0
1
M
17.664
24.73
35.328
0
1
17.664
35.328
OFF
1
0
23.552
49.46
35.328
1
0
M
17.664
49.46
35.328
1
0
1
13.248
35.328
Off
1
0
13.248
2.208
Off
1
M
13.248
24.73
35.328
1
13.248
49.46
35.328
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X2
Input
Crystal connection. Connect to a pullable crystal. See table above.
2
X1
Input
Crystal connection. Connect to a pullable crystal. See table above.
3
VDD
Power
Connect to +3.3V.
4
VIN
Input
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency.
5
NC
--
No Connect. Okay to connect to VDD or GND (to match MK3732-07).
6
GND
Power
Connect to ground.
7
CLK1
Output
Clock output #1 per table above.
8
CLK2
Output
Clock output #2 per table above.
9
S2
Input
Select input #2. Selects outputs per table above. Internal pull-up resistor.
10
OE
Input
Output enable. Tri-states outputs when low. Internal pull-up resistor.
11
S0
Input
Select input #0. Selects outputs per table above.
12
NC
--
No Connect. Okay to connect to VDD or GND (to match MK3732-07).
13
VDD
Power
Connect to +3.3V.
14
GND
Power
Connect to ground.
15
DC
-
Don’t connect. Do not connect anything to this pin.
16
S1
Input
Select input #1. Selects outputs per table above.
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相关代理商/技术参数 |
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| MK3732-19GLF | 制造商:Integrated Device Technology Inc 功能描述:MK3732-19GLF - Bulk |
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