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参数资料
| 型号： | MK3771-17ATR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 108 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封装： | QSOP-28 |
| 文件页数： | 2/4页 |
| 文件大小： | 62K |
| 代理商： | MK3771-17ATR |
MK3771-17
VCXO and HDTV Set-Top Clock Source
MDS 3771-17 B
2
Revision 091701
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126 408) 295-9800tel www.icst.com
BS0
X2
X1
VDD
VIN
VDD
CS
GND
BCLK
VS
ACLK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Assignment
AS1
AS0
VCLK2
VCLK1
GND
VCLK4
VDD
AS2
GND
VCLK3
CCLK1
BS1
CCLK2
Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections
Number
Name
Type Description
1
BS0
I
B Clock Select 0. Selects BCLK frequency. See table above. Internal pull-up.
2
X2
XO
Crystal connection. Connect to a pullable 13.5 MHz crystal.
3
X1
XI
Crystal connection. Connect to a pullable 13.5 MHz crystal.
4, 5, 7, 8, 22
VDD
P
Connect to +3.3V.
6
VIN
VI
Analog control voltage for VCXO. Pulls outputs ±100 ppm by varying from 0 to 3.3V.
9
CS
TI
Communications Clock Select. Selects CCLK 1 and 2 per table above. Internal pull-up.
10, 11,19,20,24
GND
P
Connect to ground.
12
BCLK
O
B Clock output. Determined by status of BS1, BS0.
13
VS
TI
VCXO Clock Select. Selects frequencies on VCLK1-VCLK4 per table above.
14
ACLK
O
Audio Clock output. Determined by status of AS2:0 per table above.
15
CCLK2
O
Communications Clock Output 2. Determined by status of CS per table above.
16
BS1
TI
B Clock Select 1. Selects BCLK frequency. See table above.
17
CCLK1
O
Communications Clock output 1. Determined by status of CS per table above.
18
VCLK3
O
VCXO Clock output 3. Can be either 27 or 13.5 MHz per table above.
21
AS2
I
Audio Clock Select pin 2. Selects Audio clock on pin 14 per table above. Internal pull-up.
23
VCLK4
O
VCXO Clock output 4. Can be either 27 or 108 MHz per table above.
25
VCLK1
O
VCXO Clock output pin 1. Always 27 MHz.
26
VCLK2
O
VCXO Clock output pin 2. Can be either 27 or 54 MHz per table above.
27
AS0
I
Audio Clock Select pin 0. Selects Audio clock on pin 14. See table above. Internal pull-up.
28
AS1
I
Audio Clock Select pin 1. Selects Audio clock on pin 14. See table above. Internal pull-up.
0 = connect directly to GND
M = leave unconnected (floating)
1 = connect directly to VDDIO
X = don’t care
AS2AS1AS0
ACLK
0
8.192
0
1
11.2896
0
1
0
12.288
0
1
16.9344
1
0
16.384
1
0
1
22.5792
1
0
18.432
1
24.576
Audio Clock (MHz)
VS
VCLK1
VCLK2
VCLK3
VCLK4
0
27
108
M
27
54
13.5
108
1
27
VCXO Clocks (MHz)
BS1BS0 CS
BCLK
CCLK1
CCLK2
0
74.175
20
25
0
1
74.175
11.0592
24.576
0
1
0
74.25
20
25
0
1
74.25
11.0592
24.576
M
0
5.06
20
25
M
0
1
5.06
11.0592
24.576
M
1
0
10.12
20
25
M
1
10.12
11.0592
24.576
1
0
48
20
25
1
0
M
48
7.3728
24
1
0
1
48
11.0592
24.576
1
0
14.318
20
25
1
M
14.318
7.3728
28.636
1
14.318
11.0592
24.576
B and C Clocks (MHz)
Pin Descriptions
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