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参数资料
| 型号： | MK50DX256ZCLL10R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, LQFP-100 |
| 文件页数： | 22/73页 |
| 文件大小： | 991K |
| 代理商： | MK50DX256ZCLL10R |
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Table 15. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Jcyc_pll
PLL period jitter (RMS)
fvco = 48 MHz
fvco = 100 MHz
—
120
50
—
ps
Jacc_pll
PLL accumulated jitter over 1s (RMS)
fvco = 48 MHz
fvco = 100 MHz
—
1350
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
0.15 +
1075(1/
fpll_ref)
ms
1. The startup time is defined as the time between the IRC being enabled, either by the MCG or by the IRCLKEN bit being
set, and the first edge of the internal reference clock.
2. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(
Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification was obtained at TBD frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
Table continues on the next page...
Peripheral operating requirements and behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
29
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