参数资料
型号: MK5811CMILFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 32 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件页数: 5/10页
文件大小: 234K
代理商: MK5811CMILFT
MK5811C
LOW EMI CLOCK GENERATOR
SSCG
IDT LOW EMI CLOCK GENERATOR
4
MK5811C
REV F 121409
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant crystal. To optimize the
initial accuracy, connect crystal capacitors from pins X1 to
ground and X2 to ground. The value of these capacitors is
given by the following equation:
Crystal caps (pF) = (CL - 6) x 2
In the equation, CL is the crystal load capacitance. For
example, a crystal with a 16 pF load capacitance uses two
20 pF [(16-6) x 2] capacitors.
Spread Spectrum Profile
The MK5811C is a low EMI clock generator using a
optimized frequency slew rate algorithm to facilitate down
stream tracking of zero delay buffers and other PLL devices.
Modulation Rate
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax)
and minimum frequency of the clock (fmin) determine this
band of frequencies. The time required to transition from
fmin to fmax and back to fmin is the period of the Modulation
Rate. The Modulation Rate of SSCG clocks are generally
referred to in terms of frequency, or
fmod = 1/Tmod
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
The Spread Spectrum modulation Rate, fmod, is given by
the following formula:
fmod = fin/DR
where; fmod is the Modulation Rate, fin is the Input
Frequency and DR is the Divider Ratio as given in the
“Modulation Rate Divider Ratios” table. Notice that Input
Frequency Range is set by FRSEL.
Modulation Rate Divider Ratios
Ti m e
F
requen
c
y
Modulation Rate
FRSEL
Input Freq. Range
Divider Ratio (DR)
0
4 to 8 MHz
128
1
8 to 16 MHz
256
M
16 to 32 MHz
512
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相关代理商/技术参数
参数描述
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