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参数资料
| 型号： | MK5818STR |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 16 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 3/8页 |
| 文件大小： | 179K |
| 代理商： | MK5818STR |
MK5818
SPREAD SPECTRUM CLOCK GENERATOR
SSCG
IDT / ICS SPREAD SPECTRUM CLOCK GENERATOR
3
MK5818
REV A 032206
External Components
The MK5818 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK5818. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (CL - 6) x 2
In the equation, CL is the crystal load capacitance. So, for a
crystal with a 16pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Spread Spectrum Profile
The MK5818 low EMI clock generator uses an optimized
frequency slew rate algorithm to facilitate down stream
tracking of zero delay buffers and other PLL devices. The
frequency modulation amplitude is constant with variations
of the input frequency.
Modulation Rate
The time required to transition from fMIN (minimum
frequency of the clock) to fMAX (maximum frequency of the
clock) and back to fMIN is the period of the modulation rate,
TMOD. The modulation rates of spread spectrum clock
generators are generally referred to in terms of frequency,
and fMOD = 1/TMOD.
The input clock frequency (fIN) and the internal divider
determine the modulation rate.
The spread spectrum modulation rate (fMOD) is given by the
formula fMOD = fIN/DR, where:
fMOD is the modulation rate, fIN is the input frequency, and
DR is the divider ratio (see table below).
Input Frequency Range
Divider Ratio (DR)
8 to 16 MHz
256
Ti m e
F
requen
c
y
Modulation Rate
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