参数资料
型号: MK74CB217RTR
元件分类: 时钟及定时
英文描述: CMOS SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封装: 0.150 INCH, SSOP-28
文件页数: 2/5页
文件大小: 76K
代理商: MK74CB217RTR
MK74CB217
Dual 1 to 8 Buffalo Clock Driver
MDS74CB217A
2
Revision 12299
Printed 2/22/00
IntegratedCircuit Systems, Inc. 525 Race Street San Jose CA 95126(408) 295-9800tel www.icst.com
PRELIMINARY INFORMATION
Number
Name
Type
Description
1
INA
I
Clock input for eight A outputs.
2, 3, 4
QA0, QA1, QA2
O
Clock A outputs.
5, 6
VDD
P
Power supply. Connect to 3.3 V or +5 V. Must be same as pins 23, 24.
7, 8
QA3, QA4
O
Clock A outputs.
9, 10
GND
P
Connect to ground.
11, 12, 13 QA5, QA6, QA7
O
Clock A outputs.
14
OEA
I
Output Enable. Tri-states all A clock outputs when this input is low. Internal pull-up.
15
OEB
I
Output Enable. Tri-states all B clock outputs when this input is low. Internal pull-up.
16, 17, 18 QB7, QB6, QB5
O
Clock B outputs.
19, 20
GND
P
Connect to ground.
21, 22
QB4, QB3
O
Clock B outputs.
23, 24
VDD
P
Power supply. Connect to +3.3 V or +5 V. Must be same as pins 5, 6.
25, 26, 27 QB2, QB1, QB0
O
Clock B outputs.
28
INB
I
Clock input for eight B outputs.
Pin Descriptions
Type: I = Input, O = output, P = power supply connection
Pin Assignment
1
8
9
2
3
4
5
6
7
10
11
12
13
14
QA0
QA1
QA2
QA3
QA4
QA5
QA7
QA6
INA
GND
OEA
VDD
QB0
QB1
QB2
QB3
QB4
QB5
QB7
QB6
INB
GND
OEB
VDD
16
15
17
18
19
20
21
22
23
24
25
28
27
26
Suggested Layout
V
G
V
For simplicity, terminating resistors are not shown for the
outputs, but should be placed as close to the device as
possible. It is most critical to have the 0.1F decoupling
capacitors closest.
V = connect to VDD
= connect to GND
G
0.1F
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