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参数资料
| 型号： | MK74CG117AFLF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 90 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 4/7页 |
| 文件大小： | 155K |
| 代理商： | MK74CG117AFLF |
16 Output Low Skew Clock Generator
MDS 74CG117A D
4
Revision 051304
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
MK74CG117A
Power Dissipation, Termination, and Operating
Frequency
As with all clock drivers, the power dissipated by the
MK74CG117A is affected by the external loading on
the output pins. This consists of the capacitance of the
load that is being driven, as well as the PC board trace
itself. Since this capacitance must be charged and
discharged with each cycle of the output clock, as the
frequency goes up, so does the power required.
Operating below the specified maximum output clock
frequency shown in Table 2 will keep the MK74CG117A
power dissipation within acceptable limits.
External series termination resistors must be used in
series with each output. These resistors serve two
purposes: The first is to match the source impedance
to the line (PC board trace) that is being driven. This
will minimize reflections that cause non-linear
transitions on the output clock waveform. The output
impedance of the MK74CG117A is approximately 20
;
assuming a 50
line, then a 33 resistor should be
used at each output as shown in Figure 1.
Table 1. Tri-state and Mode Select
Table 2. Multiplier Selections (Input and CLK
Frequencies in MHz)
Figure 1. External Termination
As speeds rise, the limiting factor in device operation
becomes the power generated by having a large
number of drivers in one package. Using the external
termination resistors reduces the power dissipated
within the device, allowing output frequencies up to 100
MHz.
Note that the maximum operating frequency of the
MK74CG117A is determined by the Mode selected
from Table 1 and the Multiplier selected from Table 2.
For output frequencies above 83.3 MHz, all 16 outputs
must be at the same frequency (M1=M0=1).
When operating with a combination of 1X and 0.5X
outputs, the output frequency cannot exceed 83.3 MHz.
M1
M0
Mode
at
CLK(1x)
at
CLK/2(0.5x)
Max
Output
Freq.
0
All outputs,
including
REF,
tri-stated
ZZ
0
112 @ 1x,
4 @ 0.5x
CLK1–12
CLK13–16
83.3 MHz
0.8
1
08 @ 1x,
8 @ 0.5x
CLK5–12
CLK1–4,
13–16
83.3 MHz
1.25
1
16 outputs
@ 1x
CLK1–16
None
90 MHz
S2
S1 S0 Input Multiplier
CLK Out
Comments
0
33–55
0.5
16.5–25
Divider
only; no
PLL
0
1
20–50
1
20–50
PLL
0
1
0
16–40
1.25
20–50
PLL
0
1
10–50
2
20–90
PLL
1
0
8–40
2.5
20–90
PLL
1
0
1
8–30
3.333
26.7–90
PLL
1
0
8–25
4
32–90
PLL
1
8–20
5
40–10
PLL
33 ohm
To load
MK74CG117
Output
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK74CG117AFTR | 功能描述:时钟发生器及支持产品 16 OUTPUT LOW SKEW CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK74CG117BF | 功能描述:IC CLK GEN 16OUTPUT 48-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK74CG117BFILF | 功能描述:时钟发生器及支持产品 16 OUTPUT LOW SKEW CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK74CG117BFILFTR | 功能描述:时钟发生器及支持产品 16 OUTPUT LOW SKEW CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MK74CG117BFLF | 功能描述:时钟发生器及支持产品 16 OUTPUT LOW SKEW CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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