- 您现在的位置：买卖IC网 > PDF目录65813 > MK74CG117BFT (INTEGRATED DEVICE TECHNOLOGY INC) 100 MHz, OTHER CLOCK GENERATOR, PDSO48 PDF资料下载
参数资料
| 型号： | MK74CG117BFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 4/8页 |
| 文件大小： | 199K |
| 代理商： | MK74CG117BFT |
MK74CG117B
16 OUTPUT LOW SKEW CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT 16 OUTPUT LOW SKEW CLOCK GENERATOR
4
MK74CG117B
REV D 073108
Power Dissipation, Termination, and Operating
Frequency
As with all clock drivers, the power dissipated by the
MK74CG117B is affected by the external loading on the
output pins. This consists of the capacitance of the load that
is being driven, as well as the PC board trace itself. Since
this capacitance must be charged and discharged with each
cycle of the output clock, as the frequency goes up. so does
the power required. Operating below the specified
maximum output clock frequency shown in Table 2 will keep
the MK74CG117B power dissipation within acceptable
limits.
External series termination resistors must be used in series
with each output. These resistors serve two purposes: The
first is to match the source impedance to the line (PC board
trace) that is being driven. This will minimize reflections that
cause non-linear transitions on the output clock waveform.
The output impedance of the MK74CG117B is
approximately 20
; assuming a 50 line, then a 33
resistor should be used at each output as shown in Figure 1.
Table 1. Tri-state and Mode Select
Table 2. Multiplier Selections (Input and CLK
Frequencies in MHz)
Figure 1. External Termination
As speeds rise, the limiting factor in device operation
becomes the power generated by having a large number of
drivers in one package. Using the external termination
resistors reduces the power dissipated within the device,
allowing output frequencies up to 100 MHz.
Note that the maximum operating frequency of the
MK74CG117A is determined by the Mode selected from
Table 1 and the Multiplier selected from Table 2. For output
frequencies above 83.3 MHz, all 16 outputs must be at the
same frequency (M1=M0=1).
When operating with a combination of 1X and 0.5X outputs,
the output frequency cannot exceed 83.3 MHz.
M1
M0
Mode
at
CLK(1x)
at
CLK/2(0.5x)
Max
Output
Freq.
0
All outputs,
including
REF,
tri-stated
ZZ
0
112 @ 1x,
4 @ 0.5x
CLK1–12
CLK13–16
83.3 MHz
0.8
1
08 @ 1x,
8 @ 0.5x
CLK5–12
CLK1–4,
13–16
83.3 MHz
1.25
1
16 outputs
@ 1x
CLK1–16
None
100 MHz
S2
S1 S0 Input Multiplier
CLK Out
Comments
0
33–50
0.5
16.5–25
Divider
only; no
PLL
0
1
20–50
1
20–50
PLL
0
1
0
16–40
1.25
20–50
PLL
0
1
10–50
2
20–100
PLL
1
0
8–40
2.5
20–100
PLL
1
0
1
8–30
3.333
26.7–100
PLL
1
0
8–25
4
32–100
PLL
1
8–20
5
40–90
PLL
33 ohm
To load
MK74CG117
Output
相关PDF资料 |
PDF描述 |
|---|---|
| MK74CG117BFIT | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| MK74CG117BFI | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| ML4409-30 | 75 V, SILICON, VARIABLE CAPACITANCE DIODE |
| ML4P169 | 500 V, SILICON, PIN DIODE |
| ML4P170 | 500 V, SILICON, PIN DIODE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MK74CG117BFTR | 功能描述:IC CLK GEN 16OUTPUT 48-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK74ZD133 | 制造商:ICS 制造商全称:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133F | 制造商:ICS 制造商全称:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133FT | 制造商:ICS 制造商全称:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133Y | 制造商:ICS 制造商全称:ICS 功能描述:PLL and 32-Output Clock Driver |
发布紧急采购，3分钟左右您将得到回复。