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参数资料
| 型号： | ML2037CS |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | DSP-NUM CONTROLLED OSCILLATOR, PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 5/10页 |
| 文件大小： | 213K |
| 代理商： | ML2037CS |
ML2037
4
REV. 1.0 10/10/2000
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR (Continued)
tR
CLK OUT Rise Time
CL = 25pF, See Timing Diagram 2
8
ns
tF
CLK OUT Fall Time
CL = 25pF, See Timing Diagram 2
8
ns
LOGIC
VIL
Input Low Voltage
1.0
V
VIH
Input High Voltage
DVCC - 1
V
IIL
Input Low Current
-1
A
IIH
Input High Current
1
A
VOL
Output Low Voltage
IOL = -2mA
0.4
V
VOH
Output High Voltage
IOH = 2mA
4.0
V
fS CLK
Serial Clock Frequency
0.01
10
MHz
tPW
Serial CLock Pulse Width
40
ns
tSSD
S DATA IN Setup Time
10
ns
tHSD
S DATA IN Hold Time
10
ns
tSSENS
S ENABLE Setup Time
30
ns
tSSENH
S ENABLE Hold Time
50
ns
tDSEN
Delay from S ENABLE to Stable Output
fCLK IN = 32MHz
500
ns
tDSYNC
Delay from SYNC to Output Start
fCLK IN = 32MHz
500
ns
SUPPLY
AICC
AVCC Current
fCLK IN = 16MHz
35
45
mA
fCLK IN = 32MHz
40
50
mA
SHDN = 5V
10
A
DICC
DVCC Current
fCLK IN = 16MHz
10
14
mA
fCLK IN = 32MHz
16
20
mA
SHDN = 5V
30
A
fCLK OUT
fCLK IN
tR
tF
CLK IN
CLK OUT
Timing Diagram 1.
Timing Diagram 2.
tSSENS
tSSENH
S CLK
S DATA IN
S ENABLE
tSSD
tHSD
tPW
D0
D1
D2
D14
D15
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