参数资料
型号: ML4800CS
厂商: Fairchild Semiconductor
文件页数: 11/14页
文件大小: 114K
描述: IC PFC CTRLR AVERAGE CURR 16SOIC
标准包装: 48
模式: 平均电流
频率 - 开关: 76kHz
电流 - 启动: 200µA
电源电压: 11 V ~ 16.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
PRODUCT SPECIFICATION
ML4800
REV. 1.0.5 9/25/01
11
where C
SS
 is the required soft start capacitance, and t
DELAY
 
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufcient output power for
the PWM section. The PWM start-up delay should be at least
5ms.
Solving for the minimum value of C
SS
:
Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the SS
capacitor and activation of the PWM section can result if
V
FB
 is in the hysteresis band of the V
IN
 OK comparator at
start-up. The magnitude of V
FB
 at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a
1.0礔 soft start capacitor will allow time for V
FB
 and PFC
out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.
Generating V
CC
The ML4800 is a voltage-fed part. It requires an external
15V, ?0% (or better) shunt voltage regulator, or some other
V
CC
 regulator, to regulate the voltage supplied to the part at
15V nominal. This allows low power dissipation while at the
same time delivering 13V nominal gate drive at the PWM
OUT and PFC OUT outputs. If using a Zener diode for this
function, it is important to limit the current through the
Zener to avoid overheating or destroying it. This can be
easily done with a single resistor in series with the Vcc pin,
returned to a bias supply of typically 18V to 20V. The
resistors value must be chosen to meet the operating current
requirement of the ML4800 itself (8.5mA, max.) plus the
current required by the two gate driver outputs.
EXAMPLE:
With a V
BIAS
 of 20V, a V
CC
 of 15V and the ML4800 driving
a total gate charge of 90nC at 100kHz (e.g., 1 IRF840
MOSFET and 2 IRF820 MOSFETs), the gate driver current
required is:
Choose R
BIAS
 = 240&.
The ML4800 should be locally bypassed with a 1.0礔
ceramic capacitor. In most applications, an electrolytic
capacitor of between 47礔 and 220礔 is also required across
the part, both for ltering and as part of the start-up bootstrap
circuitry.
Css    5ms
25礎
1.25V
-------------- -
?/DIV>
100nF
=
=
(6a)
I
GATEDRIVE
100kHz  90nC
?/DIV>
9mA
=
=
(7)
R
BIAS
V
BIAS
V
CC

I
CC
I
G
I
Z
+   +
---------------------------------
=
(8)
R
BIAS
20V  15V

6mA   9mA   5mA
+
+
--------------------------------------------------    250&
=
=
Figure 4. Typical Trailing Edge Control Scheme
RAMP
VEAO
TIME
VSW1
TIME
REF
EA

+

+
OSC
DFF
R
D
Q
Q
CLK
U1
RAMP
CLK
U4
U3
C1
RL
I4
SW2
SW1
+
DC
I1
I2
I3
VIN
L1
U2
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