参数资料
型号: ML4824IP1
厂商: Fairchild Semiconductor
文件页数: 9/15页
文件大小: 103K
描述: IC PFC CTRLR AVERAGE CURR 16DIP
标准包装: 25
模式: 平均电流
频率 - 开关: 76kHz
电流 - 启动: 700µA
电源电压: 10.5 V ~ 13.2 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 16-DIP(0.300",7.62mm)
供应商设备封装: 16-DIP
包装: 管件
产品目录页面: 1222 (CN2011-ZH PDF)
其它名称: ML4824IP1_NL
ML4824IP1_NL-ND
PRODUCT SPECIFICATION
ML4824
REV. 1.0.6 11/7/03
9
ML4824s voltage error amplier has a specially shaped
nonlinearity such that under steady-state operating condi-
tions the transconductance of the error amplier is at a local
minimum. Rapid perturbations in line or load conditions will
cause the input to the voltage error amplier (V
FB
) to devi-
ate from its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplier will increase
signicantly, as shown in the Typical Performance Charac-
teristics. This raises the gain-bandwidth product of the volt-
age loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with a con-
ventional linear gain characteristic.
The current amplier compensation is similar to that of the
voltage error amplier with the exception of the choice of
crossover frequency. The crossover frequency of the current
amplier should be at least 10 times that of the voltage
amplier, to prevent interaction with the voltage loop. It
should also be limited to less than 1/6th that of the switching
frequency, e.g. 16.7kHz for a 100kHz switching frequency.
There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplier, to
increase its speed of response to current-loop perturbations.
However, the boost inductor will usually be the dominant
factor in overall current loop response. Therefore, this con-
touring is signicantly less marked than that of the voltage
error amplier. This is illustrated in the Typical Performance
Characteristics.
For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information for
the design of this class of PFC.
Oscillator (RAMP 1)
The oscillator frequency is determined by the values of R
T
 
and C
T
, which determine the ramp and off-time of the
oscillator output clock:
The deadtime of the oscillator is derived from the following
equation:
at V
REF
 = 7.5V:
The deadtime of the oscillator may be determined using:
The deadtime is so small (t
RAMP
 >> t
DEADTIME
) that the
operating frequency can typically be approximated by:
EXAMPLE:
For the application circuit shown in the data sheet, with the
oscillator running at:
Solving for R
T
 x C
T
 yields 2 x 10
-4
. Selecting standard
components values, C
T
 = 470pF, and R
T
 = 41.2k&.
The deadtime of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator deadtime, the Maximum PWM Duty Cycle is
typically 45%. In many applications, care should be taken
that C
T
 not be made so large as to extend the Maximum
Duty Cycle beyond 50%. This can be accomplished by using
a stable 470pF capacitor for C
T
.
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4824 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at the PFC frequency in the ML4824-1, and at twice
the PFC frequency in the ML4824-2). The PWM is capable
of current-mode or voltage mode operation. In current-mode
applications, the PWM ramp (RAMP 2) is usually derived
directly from a current sensing resistor or current trans-
former in the primary of the output stage, and is thereby
representative of the current owing in the converters output
stage. DC I
LIMIT
, which provides cycle-by-cycle current
limiting, is typically connected to RAMP 2 in such applica-
tions. For voltage-mode operation or certain specialized
applications, RAMP 2 can be connected to a separate RC
timing network to generate a voltage ramp against which
VDC will be compared. Under these conditions, the use of
voltage feedforward from the PFC buss can assist in line
regulation accuracy and response. As in current mode
operation, the DC I
LIMIT
 input is used for output stage
overcurrent protection.
No voltage error amplier is included in the PWM stage of
the ML4824, as this function is generally performed on the
output side of the PWMs isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWMs RAMP 2 input which allows V
DC
 
to command a zero percent duty cycle for input voltages
below 1.25V.
PWM Current Limit
The DC I
LIMIT
 pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output ip-op is reset by the clock
pulse at the start of the next PWM power cycle.
f
OSC
1
t
RAMP
t
DEADTIME
+
-------------------------------------------------- -
=
(2)
t
RAMP
C
T
R
T
?/DIV>
In
V
REF
1.25

V
REF
3.75

------------------------------- -
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
(3)
t
RAMP
C
T
R
T
?/DIV>
0.51
?/DIV>
=
t
DEADTIME
2.5V
5.1mA
----------------- -   C
T
?/DIV>
490   C
T
?/DIV>
=
=
(4)
f
OSC
1
t
RAMP
--------------- -
=
(5)
f
OSC
100kHz
1
t
RAMP
--------------- -
=
=
t
RAMP
C
T
R
T
?/DIV>
0.51
?/DIV>
1   10
5

?/DIV>
=
=
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