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参数资料
| 型号： | ML6673CQ |
| 英文描述： | Fast Ethernet/FDDI TP-PMD Transceiver |
| 中文描述： | 快速以太网/ FDDI的物理介质收发器 |
| 文件页数： | 2/8页 |
| 文件大小： | 183K |
| 代理商： | ML6673CQ |
ML6673
2
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
4
3
2
1
32 31 30
RXOUT+
RVCCD
SD–
SD+
N/C
TGNDD
LPBK
TXOFF
N/C
RRSET1
RRSET2
N/C
RGND
N/C
TVCCA
TGNDA
TXIN+
TXIN–
TVCCD
RTSET1
RTSET2
TPOUT+
TPOUT–
RXOUT
–
RVCCA
N/C
CMREF
TPIN+
TPIN–
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
121314
15
16
32
31
30
29
28
27
26
25
TPOUT–
TPOUT+
RTSET2
RTSET1
TVCCD
TXIN–
TXIN+
N/C
RRSET1
TPIN–
TPIN+
CMREF
N/C
RVCCA
RXOUT–
RXOUT+
RVCCD
SD–
SD+
N/C
TGNDD
LPBK
TXOFF
RRSET2
N/C
RGND
N/C
TVCCA
TGNDA
ML6673
32-Pin PCC (Q32)
ML6673
32-Pin TQFP (H32-7)
PIN CONFIGURATION
NAME
FUNCTION
NAME
FUNCTION
TXIN+, TXIN–
These differential ECL100K compatible
inputs receive NRZI data from the PHY
for transmission.
TPOUT+,
Outputs from the NRZI-MLT3 state
TPOUT–
machine drive these differential current
outputs. The transmitter filter/transformer
module connects the media to these pins.
LPBK
This TTL input enables transmitter-
receiver loopback internally when
asserted low. When LPBK is asserted,
signal detect is asserted.
TXOFF
This TTL input forces the NRZI-MLT3
state machine to a high impedence state
when asserted low and shuts off transmit
bias current.
RTSET1,
An external 1% resistor connected
RTSET2
between these pins controls the
transmitter output current amplitude.
IOUT = 64 x 1.25V/RTSET
TVCCA,
Separate analog and digital transmitter
TVCCD
power supply pins help to isolate
sensitive circuitry from noise generating
digital functions. Both supplies are
nominally +5 volts.
PIN DESCRIPTION
TGNDA,
Analog and digital transmitter grounds
TGNDD
provide separate return paths for clean
and noisy signals.
SD+, SD–
These differential ECL100K compatible
outputs indicate the presence of a data
signal with an amplitude exceeding a
preset threshold.
TPIN+, TPIN–
MLT-3 encoded data from the receiver
filter/transformer module enters the
receiver through these pins.
RXOUT+,
Differential ECL100K compatible outputs
RXOUT–
provide NRZI encoded data to the PHY.
RRSET1,
Internal time constants controlling the
RRSET2
equalizer’s transfer function are set by an
external resistor connected across these
pins.
CMREF
This pin provides a DC common mode
reference point for the receiver inputs.
RVCCA,
Analog and digital supply pins are
RVCCD
separated to isolate clean and noisy
circuit functions. Both supplies are
nominally +5 volts.
RGND
Receiver ground.
相关PDF资料 |
PDF描述 |
|---|---|
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| ML6694CH | 100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CQ | XC95108-10TQ100C - NOT RECOMMENDED for NEW DESIGN |
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