- 您现在的位置：买卖IC网 > PDF目录296572 > ML6692CQ 100BASE-TX Physical Layer with MII PDF资料下载
参数资料
| 型号： | ML6692CQ |
| 英文描述： | 100BASE-TX Physical Layer with MII |
| 中文描述： | 100BASE - TX的物理层与信息产业部 |
| 文件页数： | 2/21页 |
| 文件大小： | 325K |
| 代理商： | ML6692CQ |
ML6692
10
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MDC-MDIO (MII MANAGEMENT INTERFACE)
tSPWS
Write Setup Time, MDIO Data
10
ns
Valid to MDC Rising Edge
1.4V Point
tSPWH
Write Hold Time, MDIO Data
10
ns
Valid After MDC Rising Edge
1.4V Point
tSPRS
Read Setup Time, MDIO Data
100
ns
Valid to MDC Rising Edge
1.4V Point
tSPRH
Read Hold time, MDIO Data
0
ns
Valid After MDC Rising Edge
1.4V Point
tCPER
Period of MDC
400
ns
tCPW
Pulsewidth of MDC
Positive or negative pulses
160
ns
INITIALIZATION INTERFACE
tPW1
ECLK Positive Pulsewidth
EDIN floating (EEPROM Mode)
900
ns
tPW2
ECLK Negative Pulsewidth
EDIN floating (EEPROM Mode)
900
ns
tPER1
ECLK Period, EEPROM Mode
EDIN floating (EEPROM Mode)
1800
ns
tDV1
EDOUT Data Valid Time After
EDIN floating (EEPROM Mode)
900
ns
ECLK Rising Edge
tPER2
ECLK period
EDIN high (Microcontroller Mode)
5000
ns
tPW3
ECLK Positive Pulsewidth
EDIN high (Microcontroller Mode)
2000
ns
tPW4
ECLK Negative Pulsewidth
EDIN high (Microcontroller Mode)
2000
ns
tS1
ECLK Data Setup Time
EDIN high (Microcontroller Mode)
10
ns
tH1
ECLK Data Hold Time
EDIN high (Microcontroller Mode)
10
ns
Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Note 2. Measured using the test circuit shown in fig. 1, under the following conditions:
RLP = 200W, RLS = 49.9W, RTSET = 2.49kW.
All resistors are 1% tolerance.
Note 3. Output current amplitude is IOUT = 40W 1.25V/RTSET.
Note 4. Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence.
Note 5. Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal
voltage. The times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the
effects of the external network coupling transformer and EMI/RFI emissions filter.
Note 6. Differential test load is shown in fig. 1 (see note 2).
Note 7. Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The
adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to
either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge.
Note 8. From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI.
Note 9. From first bit of J at the MDI, to CRS.
Note 10. From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high.
相关PDF资料 |
PDF描述 |
|---|---|
| ML6694CH | 100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CQ | XC95108-10TQ100C - NOT RECOMMENDED for NEW DESIGN |
| ML6695CQ | 100BASE-X Fiber Physical Layer With 5-bit Interface |
| ML925J40F-11 | 1610 nm, LASER DIODE |
| MLF0805-082M | 1 ELEMENT, 0.082 uH, FERRITE-CORE, GENERAL PURPOSE INDUCTOR, SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ML6694 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CH | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6694CQ | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:100BASE-TX Physical Layer with 5-Bit Interface |
| ML6695 | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer With 5-bit Interface |
| ML6695CQ | 制造商:MICRO-LINEAR 制造商全称:MICRO-LINEAR 功能描述:100BASE-X Fiber Physical Layer With 5-bit Interface |
发布紧急采购，3分钟左右您将得到回复。