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参数资料
| 型号： | ML674001TC |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, MROM, 33.333 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件页数： | 13/19页 |
| 文件大小： | 645K |
| 代理商： | ML674001TC |
Oki Semiconductor 3
ML674001/ML67Q4002/ML67Q4003
April 2004, Rev 2.0
Functional Description
CPU
Built-in Memory
Interrupt Controller
Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as inter-
rupt input signals. The interrupt controller controls these interrupt signals
going to ARM core.
1. Interrupt sources
- FIQ: 1 external source (external pin: EFIQ_N)
- IRQ: Total of 27 sources. 23 internal sources, and 4 external sources
(EXINT[3:0])
2. Interrupt priority level
- Congurable, 8-level priority for each source
3. External interrupt pin input
- EXINT[3:0] Can be set as Level or Edge sensing
- Congurable High or Low when Level sensing. Congurable Rising- or
Falling-edge triggering when Edge sensing. EFIQ_N is set as Falling-Edge
triggering.
Timer
Seven channels of 16-bit reload timers are employed. Of these, 1 channel is
used as system timer for OS.
The timers of other 6 channels are used in application software.
1. System timer: 1 channel
- 16-bit auto reload timer: Used as system timer for OS. Interrupt request
by timer overow.
2. Application timer: 6 channels
- 16-bit auto reload timer
-One shot, interval
- Clock can be independently set for each channel
Watch Dog Timer
Functions as an interval timer or a watch dog timer.
16-bit timer
Watch dog timer or interval timer mode can be selected
Interrupt reset generation
Maximum period: longer than 200 msec
Serial Interface
This MCU contains four serial interfaces.
1. SIO without FIFO: 1 channel
This is the serial port which performs data transmission, taking a synchro-
nization per character.
Selection of various parameters, such as addition of data length, a stop
bit, and a parity bit, is possible.
- Asynchronous full duplex operation
- Sampling Rate = Baud rate x 16 samples
- Character Length: 7, 8 bit
- Stop Bit Length: 1, 2 bit
-Parity: Even, Odd, none
- Error Detection: Parity, Framing, Over run
- Loop Back Function: ON/OFF, Parity, framing, Over run Compulsive
addition
- Built-in Baud Rate Generator (8-bit counter) - Independent from a bus
clock
- Internal-Baud-Rate-Clock-Stop at the Time of HALT Mode.
2. UART with 16-byte FIFO: 1 channel
Features 16-byte FIFO in both send and receive. Uses the industry stan-
dard 16550A ACE (Asynchronous Communication Element).
- Asynchronous full duplex operation
- Reporting function for all status
- 16-Byte Transmit FIFO
- 16-Byte Receive FIFO
-Transmission, reception, interrupt of line status Data set and Indepen-
dent FIFO control.
-Modem control signals: CTS, DCD, DSR, DTR, RI and RTS
- Data length: 5, 6, 7, or 8 bits
- Stop bit length: 1, 1.5, or 2 bits
- parity: Even, Odd, or none
- Error Detection: Parity, Framing, Overrun
- Built-in Baud Rate Generation
3. Synchronous serial interface: 1 channel
Clock-synchronous 8 bit serial port
- selectable 1/8, 1/16 or 1/32 of the system clock frequency.
- LSB First or MSB First.
-Master / Slave Mode
-Transceiver buffer empty interrupt
- Loopback Test Function
4. I2C: 1 channel
Based on the I2C Bus specication. Operates as a single master device.
- Communication mode: Master transmitter /master receiver
-Transmission Speed: 100 kbps (Standard mode) / 400 kbps (Fast mode)
- Addressing format: 7-bit / 10-bit
- Data buffer: 1 Byte (1 step)
- Communication Voltage: 2.7 V to 3.3 V
CPU core:
ARM7TDMI
Operating frequency:
1 MHz to 33 MHz (max)
Instructions:
ARM instruction (32-bit length) and Thumb
instruction (16-bit length) can be mixed
General register bank:
31 x 32 bits
Built-in barrel shifter:
ALU and barrel shift operations can be executed
by one instruction.
Multiplier:
32 bits x 8 bits (Modied Booth’s Algorithm)
Built-in debug function: JTAG interface, break point register
Byte Ordering:
Little Endian
FLASH ROM:
ML674001 is the ROM-less version
ML67Q4002: 256 KBytes (128K x 16 bits)
ML67Q4003: 512 KBytes (256K x 16 bits)
Access timing of this FLASH memory is congured by the
ROM bank control register of the external memory
controller.
SRAM: 32KB
(8K x 32 bits)
Read access (8/16/32 bit): 1 cycle
Write access (32 bit): 1 cycle
Write access (8/16 bit): 2 cycle
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ML675001 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:32-bit ARM-Based General-Purpose Microcontroller |
| ML675001ALAZ03A | 制造商:ROHM Semiconductor 功能描述:ARM7TDMI 32-BIT MCU 60 MHZ ROH |
| ML675001ATC | 制造商:ROHM Semiconductor 功能描述: |
| ML675001ATCZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML675001LA | 制造商:ROHM Semiconductor 功能描述: |
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