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参数资料
| 型号： | ML675001TC |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 60 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件页数： | 14/20页 |
| 文件大小： | 650K |
| 代理商： | ML675001TC |
Oki Semiconductor 3
ML675001/ML67Q5002/ML67Q5003
April 2004, Rev 2.0
Functional Description
CPU
Built-in Memory
Interrupt Controller
Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as inter-
rupt input signals. The interrupt controller controls these interrupt signals
going to ARM core.
1. Interrupt sources
- FIQ: One external source (external pin: EFIQ_N)
- IRQ: Total of 27 sources. 23 internal sources, and 4 external sources
(External pins EXINT[3:0])
2. Interrupt priority level
- Congurable, 8-level priority for each source
3. External interrupt pin input
- EXINT[3:0] can be set as Level or Edge sensing
- Congurable High or Low when Level sensing. Congurable Rise or Fall-
ing edge triggering when Edge sensing.
- EFIQ_N is set as Falling edge triggering.
Timers
The MCU contains seven 16-bit reload timers. Of these, 1 timer is used as sys-
tem timer for operating system. The other 6 timers are used by application
software.
1. System timer: 1 channel
- 16-bit auto reload timer: Used as system timer for OS. Interrupt request
by timer overow.
2. Application timer: six channels
- 16-bit auto reload timer. Interrupt request by compare match.
-One shot, interval
- Clock can be independently set for each channel
Watch Dog Timer
Functions as an interval timer or a watch dog timer.
16-bit timer
Watch dog timer or interval timer mode can be selected
Interrupt reset generation
Maximum period: longer than 200 msec
Serial Interface
The ML675001/Q5002/Q5003 contains four serial interfaces.
1. SIO without FIFO: 1 channel
This is the serial port which performs data transmission, taking a synchro-
nization per character. Selection of various parameters, such as addition
of data length, a stop bit, and a parity bit, is possible.
- Asynchronous full duplex operation
- Sampling Rate = Baud rate x 16 samples
- Character Length: 7, 8 bit
- Stop Bit Length: 1, 2 bit
-Parity: Even, Odd, none
- Error Detection: Parity, Framing, Over run
- Loop Back Function: ON/OFF, Parity, framing, Over run Compulsive
addition
- Baud Rate Generation: Exclusive baud rate generator built-in (8-bit
counter) Independent from a bus clock
- Internal-Baud-Rate-Clock-Stop at the Time of HALT Mode.
2. UART with 16-byte FIFO: 1 channel
Features 16-byte FIFO in both send and receive. Uses the industry stan-
dard 16550A ACE (Asynchronous Communication Element).
- Asynchronous full duplex operation
- Reporting function for all status
- 16 Byte transmission and reception FIFO
-Transmission, reception, interrupt of line status Data set and Indepen-
dent FIFO control.
-Modem control signals: CTS, DCD, DSR, DTR, RI and RTS
- Data length: 5, 6, 7, or 8 bits
- Stop bit length: 1, 1.5, or 2 bits
- parity: Even, Odd, or none
- Error Detection: Parity, Framing, Overrun
- Baud Rate Generation: Exclusive baud rate generator built-in
3. Synchronous serial interface: 1 channel
Clock-synchronous 8-bit serial port
- selectable 1/8, 1/16 or 1/32 of the system clock frequency.
- LSB First or MSB First.
-Master / Slave Mode
-Transceiver buffer empty interrupt
- Loopback test function
4. I2C: 1 channel
Based on the I2C Bus specication. Operates as a single master device.
- Communication mode: Master transmitter /master receiver
-Transmission Speed: 100 kbps (Standard mode) / 400 kbps (Fast mode)
- Addressing format: 7 bit / 10 bit
- Data buffer: 1 Byte (1step)
- Communication Voltage: 2.7 V to 3.3 V
CPU core:
ARM7TDMI
Operating
frequency:
1 MHz to 60 MHz (max)
Byte Ordering:
Little endian.
Instructions:
ARM instruction (32-bit length) and Thumb instruction
(16-bit length) can be mixed
General register
bank:
31 registers x 32 bits
Built-in barrel
shifter:
ALU and barrel shift operations can be executed by one
instruction.
Multiplier:
32 bits x 8 bits (Modied Booth’s Algorithm)
Built-in debug
function:
JTAG interface, break point register
FLASH ROM:
ML675001: ROM-less version
ML67Q5002: 256 Kbytes (128K x 16 bits)
ML67Q5003: 512 Kbytes (256K x 16 bits)
Access timing of this FLASH memory is congured by the
ROM bank control register of the external memory
controller.
SRAM:
32KB (8K x 32bits)
Connected to processor bus (1-cycle read, 2-cycle write)
Cache memory:
8K unied memory with 4-way set-associative
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