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参数资料
| 型号： | ML67Q4002LA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 33.333 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封装： | 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 |
| 文件页数： | 7/19页 |
| 文件大小： | 645K |
| 代理商： | ML67Q4002LA |
Oki Semiconductor 15
ML674001/ML67Q4002/ML67Q4003
April 2004, Rev 2.0
Electrical Characteristics
Absolute Maximum Ratings [1]
1.
Exceeding these maximum ratings could cause damage or lead to permanent deterioration of the device.
Item
Symbol
Conditions
Rating
Unit
Digital power supply voltage (core)
VDD_CORE
GND = AGND = 0 V
TA = 25°C
-0.3 to +3.6
V
Digital power supply voltage (I/O)
VDD_IO
-0.3 to +4.6
Input voltage
VI
-0.3 to VDD_IO+0.3
Output voltage
VO
-0.3 to VDD_IO+0.3
Analog power supply voltage
AVDD
-0.3 to VDD_IO+0.3
Analog reference voltage
VREF
-0.3 to (VDD_IO + 0.3) and -0.3 to (AVDD + 0.3)
Analog input voltage
VAI
-0.3 to VREF
Input current
II
-10 to +10
mA
Output current [2]
2.
All output pins except XA[15:0]
IO
-20 to +20
Output current [3]
3.
XA[15:0]
-30 to +30
Power dissipation
PD
LFBGA, TA = 85°C
680
mW
LQFP, TA = 85°C
1000
mW
Storage temperature
TSTG
—
-50 to +150
°C
Recommended Operating Conditions
(GND = 0 V)
Item
Symbol
Conditions
Minimum
Typical
Maximum
Unit
Digital power supply voltage (core)
VDD_CORE
VDD_IO ≥ VDD_CORE
2.25
2.5
2.75
V
Digital power supply voltage (I/O)
VDD_IO
3.0
3.3
3.6
Analog power supply voltage
AVDD
AVDD = VDD_IO
3.0
3.3
3.6
Analog reference voltage
VREF
VREF = AVDD = VDD_IO
3.0
3.3
3.6
Operating frequency [1]
fOP
VDD_CORE = 2.25 to 2.75 V,
VDD_IO = 3.0 to 3.6 V
1—
33.333
MHz
Ambient temperature
TA
—
-40
25
+85
°C
1.
Oscillator frequencies between 16 MHz and 33 MHz. Minimum of 2.56 MHz for external SDRAM. Minimum of 6.4 MHz for external EDO-DRAM. Minimum of 2 MHz for analog-to-digital converter
DC Characteristics
(VDD_CORE = 2.25 to 2.75 V, VDD_IO = 3.0 to 3.6 V, TA = -40 to +85°C)
Item
Symbol
Conditions
Minimum
Typical
Maximum
Unit
High level input voltage
VIH
—
0.8VDD_IO
—VDD_IO + 0.3
V
Low level input voltage
VIL
-0.3
—
0.2VDD_IO
Schmitt input buffer threshold voltage
VT+
—
1.6
2.1
VT-
0.7
1.1
—
VHYS
0.4
0.5
—
High level output voltage
VOH
IOH = -100 A
VDD – 0.2
—
IOH = -4 mA
2.35
—
Low level output voltage
VOL
IOL = 100 A
—
0.2
VOL
[1]
IOL = 4 mA
—
0.45
VOL
[2]
IOL = 6 mA
—
0.45
Input leak current [3]
IIH/IIL
[4]
VI = 0 V to VDD_IO
-50
—
50
A
IIL
[5]
VI = 0 V, Pull-up resistance of 50 kOhm
-200
-66
-10
II
[6]
VI = 0V to AVDD
-5
—
5
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