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参数资料
| 型号： | ML67Q4061HA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA64 |
| 封装： | 5.09 X 4.84 MM, 0.50 MM PITCH, PLASTIC, WCSP-64 |
| 文件页数： | 23/26页 |
| 文件大小： | 364K |
| 代理商： | ML67Q4061HA |
ML67Q4050/Q4060 Series
Pin Configuration
6 Oki Semiconductor
June 2006, Rev 1.2
Figure 2. 84-Pin Plastic LFBGA
NOTES:
1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See “Pin Descriptions”
Table for details.
2. NC balls can be connected to VDD_IO or GND.
ML67Q4060/61
84-Pin LFBGA
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
VDD_IO
PB1/
/RX0
PE4/
SD
PF2/
TIMER2/
CTS1
PF5/
TIMER5/
EXINT5
NC
VDD_CORE
GND
NC
VDD_IO
PC0/
MISO0/
DSR0
BOOTCLK/
PD5
PC1/
MOSI0/
DTR0
PC2/
SCK0/
RI0
VDD_IO
PC4/
MISO1/
DSR1
PC5/
MOSI1/
DTR1
PC3/
SSN0/
DCD0
GND
RESET_N
PC6/
SCK1/
RI1
PC7/
SSN1/
DCD1
RSTOUT_N/PA6/
MCLK
VDD_IO
PE5/
WS
BS/
PD4
PB0/
TX0
BOOT0/
PE3/
MCLK
PF[1[/
TIMER1/
RTS0
PF4/
TIMER4/
EXINT4
GND
PB2/
TX1/
EFIQ_N
PF0/
TIMER0/
CTS0
PF3/
TIMER3/
RTS1
RTCCLK_N
GND
TCK/
PA0
TDO/
PA3
VDD_PLL
GND
SYSCLK_N
TDI/
PA2
RTCCLK_P
SYSCLK_P
TMS/
PA1
VDD_IO
NTRST/
PA4
VDD_CORE
PE6/
SCK
JTAGE/
PA5
NC
GND
NC
PB3/
RX1/
EXINT1
NC
VDD_CORE
VDD_IO
PB4/
SCL/
TXD
PB5/
SDA/
RXD
PE1
PE0
GND
VDD_IO
GND
PE2
PD2/
AIN2
PD0/
AIN0/
EXINT2
PD1/
AIN1/
EXINT3
TEST2
PD3/
AN3
TEST1
NC
GND
GND_PLL
NC
GND_PLL
VDD_CORE
VDD_IO
VDD_PLL
JK
GH
F
E
D
C
AB
JK
GH
F
E
D
C
AB
1
2
3
4
5
6
7
8
9
10
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